Fractional-PLL Spread Spectrum Clocking for Low-Jitter EMI Control
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Solution Overview
Problem
Existing clock generators for reducing Electromagnetic Interference (EMI) in semiconductor chips face challenges such as sharp phase changes causing additional EMI components and jitters, and are vulnerable to digital noise, making them difficult to implement in large-scale microprocessors without additional noise suppression means.
Innovation Solution
A spread spectrum clock generator using a phase locked loop (PLL) with a fractional divider, a signal generator, filter, and quantizer to control the division number and suppress high-frequency noise components, eliminating the need for precise analog circuits and enabling integration into microprocessors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a stable reference clock is used to generate high-frequency clock, then clock stability is improved, but electromagnetic interference increases
Solution Approach 1:
The patent applies periodic frequency modulation to the reference clock signal, causing the clock frequency to vary periodically around a central value. This periodic variation spreads the spectral energy over a wider bandwidth, reducing peak electromagnetic interference while maintaining average clock stability for digital logic operation.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal dynamically through modulation. By varying the frequency around a nominal value according to a predetermined pattern (such as spread spectrum coding), the system reduces electromagnetic radiation intensity at any single frequency while maintaining overall clock functionality.
2Object-generated harmful factors
If lookup table with sine function is used to modulate clock frequency, then electromagnetic interference is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces analog sine wave generation circuits with digital lookup table implementation. Instead of using precision analog oscillators and function generators, the system uses digital memory (lookup table) storing pre-computed sine values, which are then converted to control signals for frequency modulation. This substitution eliminates the need for high-precision analog components.
Solution Approach 2:
The patent uses a digital copy of the sine function stored in lookup table memory rather than generating the actual analog sine wave. The digital representation of sine values is used to control the frequency modulation, avoiding the need for precision analog circuitry while achieving the same spectral spreading effect.
3Measurement precision
If fractional division number is used in PLL, then clock frequency accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces a fractional divider as an intermediary component between the PLL voltage-controlled oscillator and the feedback path. This fractional divider enables precise frequency control by allowing non-integer division ratios, which would be difficult to achieve with traditional integer dividers. The fractional divider acts as a mediator that translates control signals into precise frequency adjustments.
Solution Approach 2:
The patent segments the frequency division function into multiple stages, including integer division and fractional division components. By breaking down the frequency control into separable functions (integer part and fractional part), the system achieves high precision frequency control while keeping each individual component relatively simple and manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces EMI components and jitters by controlling the division number and suppressing noise, allowing for broader integration into semiconductor chips and reducing EMI by 20-30 dB, while avoiding the use of high-precision analog circuits.
Implementation Method 1
A spread spectrum clock generator according to the present invention comprises a phase locked loop (PLL) which comprises a phase comparator to which a reference clock is input
Implementation Method 2
a voltage control oscillator which generates an oscillation frequency that is variable in response to the phase comparator output
Implementation Method 3
a filter which is connected to the signal generator output to suppress high frequency components of noise included in the signal
Data Source
AI summary
The present invention provides a spread spectrum clock generator that is capable of preventing phase jumps and jitters and suppressing the occurrence of Electro Magnetic Interference components and that can easily be applied to large scale integrated circuits. The spread spectrum clock generator can be configured with a filter, quantizer, fractional divider, and other elements. Also, this clock generator circuitry can be configured by combination of a delta-sigma ΔΣ quantizer and factional divider so that sine wave modulation and random number modulation can be realized. Thereby, control with digital values can be performed. This clock generator prevents precipitous phase variations in the output high frequency clock and makes fine phase control possible. Consequently, EMI reduction by 20-30 dB can be expected.