Fractional-N PLL Reference Counter for Phase-Coherent Switching
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Solution Overview
Problem
Fractional-n phase locked loops (PLLs) face challenges in maintaining phase coherency when switching between frequencies, leading to phase differences between originally-generated and subsequently-generated signals, which complicates phase alignment in multiple PLL systems and is exacerbated by the power consumption issues in direct digital synthesis.
Innovation Solution
Multiplying the output of a reference counter by a fractional divide control number ensures that the carry bit timing is consistent, maintaining phase coherency between originally-generated and subsequently-generated signals by using a reference counter that increments with each clock pulse, thus controlling the duty cycle effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional accumulator is used to control duty cycle by adding a number, then frequency resolution is improved, but phase coherency deteriorates when switching between frequencies
Solution Approach 1:
A reference counter is introduced as an intermediary component that generates reference counts synchronized to the reference frequency. This reference counter mediates between the frequency control mechanism and the accumulator, providing a stable timing reference that ensures phase coherency is maintained when switching between different frequency values in fractional-n PLL operation.
Solution Approach 2:
The system implements feedback by comparing the accumulator output with the reference counter output. The reference counter provides a feedback mechanism that ensures the duty cycle control maintains phase alignment with the reference frequency, preventing phase drift when switching between frequencies while preserving fine frequency resolution.
2Stability of the object's composition
If phase resync system with periodic pulses is employed to preserve coherency, then phase coherency is improved, but spurs are introduced and pulse timing regulation complexity increases
Solution Approach 1:
The harmful periodic pulse injection mechanism is extracted and replaced with a cleaner approach. Instead of injecting external periodic pulses that cause spurs, the system uses the naturally occurring reference counter output in conjunction with the accumulator to control duty cycle, eliminating the source of spur generation while maintaining phase coherency.
Solution Approach 2:
The reference counter creates a copied timing signal that mirrors the reference frequency phases. This copied timing reference is used to control the duty cycle switching, ensuring that phase relationships are preserved without introducing external periodic pulses that would generate spurs in the output spectrum.
3Stability of the object's composition
If direct digital synthesis is used to provide phase coherency, then phase coherency is improved, but power consumption increases significantly
Solution Approach 1:
Instead of using complex direct digital synthesis hardware that consumes significant power, the system employs simple counter and accumulator circuits that are computationally lightweight. The reference counter and accumulator use minimal logic resources and consume far less power, providing an energy-efficient alternative that maintains phase coherency through simple digital counting rather than complex DDS algorithms.
Solution Approach 2:
The patent replaces the mechanical/computational complexity of direct digital synthesis with a simpler digital counting mechanism. The reference counter and accumulator system substitutes for the complex DDS phase accumulator and sine lookup tables, achieving phase coherency through basic digital arithmetic operations that consume minimal power compared to full DDS implementation.
Data Source
AI summary
In a fractional-n Phase Locked Loop the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+1 switching.