Fractional PLL Tuning With Dithered Division Ratio
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Solution Overview
Problem
Switch mode power supply signals emit significant noise, which can negatively impact EMI-sensitive applications, and existing PLLs have limited bandwidth and tuning range, restricting their ability to accommodate a wide range of input frequencies.
Innovation Solution
A tunable fractional phase locked loop (PLL) that includes a controller with a tuning module, dither signal generator, and sigma delta modulator, allowing it to generate a dithered division ratio to tune itself to a wide range of input frequencies, utilizing a high frequency VCO without the limitations of traditional PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a traditional PLL is used with frequency dithering, then noise spectral content is spread over a frequency band, but the bandwidth is limited by the PLL components
Solution Approach 1:
The patent implements a dynamically adjustable division ratio in the feedback path that can be tuned in real-time. The division ratio is modified by adding a dither signal to create a time-varying feedback division ratio, allowing the PLL to adapt its bandwidth and frequency response dynamically. This resolves the contradiction by enabling both noise spreading and extended frequency bandwidth through dynamic parameter adjustment.
Solution Approach 2:
The patent changes the division ratio parameter in the feedback path by introducing a dither signal. This parameter change allows the PLL to operate with an effective division ratio that varies over time, thereby spreading the noise spectral content while simultaneously extending the usable frequency bandwidth beyond what a fixed division ratio would permit.
2Adaptability or versatility
If a high frequency VCO is used to accommodate high input frequencies, then the input frequency range is extended, but the oscillator bandwidth becomes narrow
Solution Approach 1:
The patent employs a feedback mechanism where the division ratio is continuously adjusted based on the phase detector output. The feedback path includes a dither signal generator that modifies the division ratio to compensate for the narrow bandwidth of high-frequency VCOs, thereby maintaining both extended input frequency range and adequate oscillator bandwidth through active feedback control.
Solution Approach 2:
The patent makes the feedback division ratio dynamic by introducing time-varying dither signals. This dynamic adjustment allows the system to maintain optimal performance across a wide input frequency range while compensating for the inherently narrow bandwidth of high-frequency VCOs through real-time parameter modulation.
3Object-affected harmful factors
If frequency dithering is applied to spread spectral content, then noise magnitude is reduced, but the PLL requires precise control to maintain locking
Solution Approach 1:
The patent uses feedback control to maintain PLL locking stability despite frequency dithering. The phase detector continuously monitors the phase difference between the VCO output and reference signal, and the feedback path adjusts the division ratio to compensate for dither-induced frequency variations, thereby maintaining lock while preserving noise reduction benefits.
Solution Approach 2:
The patent applies preliminary dithering to the division ratio before the signal passes through the PLL loop. By pre-modulating the division ratio with a dither signal, the system proactively spreads the noise spectral content while the subsequent feedback mechanism ensures stability is maintained, preventing locking issues before they occur.
Data Source
AI summary
A tunable fractional phase locked loop (PLL) (hereinafter “tunable PLL”) is described herein and includes a controller configured to tune the tunable PLL to a range of frequencies corresponding to a frequency of the input clock signal. The tunable PLL includes a phase detector configured to receive an input clock signal and a feedback signal, a voltage controller oscillator (VCO) configured to receive the error signal from said phase detector and in response thereto to generate a VCO clock signal, a controller configured to generate a dithered division ratio having an average value corresponding to a ratio of a number of edges of the VCO clock signal generated in a cycle of the input clock signal, and a feedback module configured to generates a feedback signal to tune the PLL such that the PLL operates in the range of input frequencies of the input clock signal.