Fractional-N PLL Architecture Without a Multi-Modulus Divider
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fractional-N PLL frequency synthesizers are challenging to design due to the complexity of the delta-sigma modulator and multi-modulus divider circuits, which limits the simplicity and efficiency of frequency switching and resolution.
Innovation Solution
A simplified fractional-N PLL frequency synthesizer is proposed, utilizing a delta-sigma modulator with a numeric counter to determine the fractional frequency division ratio, eliminating the need for a multi-modulus divider and incorporating a pre-scaler to enhance circuit simplicity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional fractional-N PLL frequency synthesizer uses a delta-sigma modulator and multi-modulus divider, then frequency resolution is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex multi-modulus divider from the conventional fractional-N PLL architecture. Instead of using a multi-modulus divider combined with delta-sigma modulation, the invention employs a simplified integer divider that operates with a fixed division ratio, thereby achieving frequency resolution improvement without the associated circuit complexity
Solution Approach 2:
The patent inverts the conventional approach by placing the delta-sigma modulator in the feedback path rather than in the forward path. The modulator receives the divided feedback signal and generates an overflow signal that controls the phase frequency detector, effectively achieving fractional frequency synthesis through a different architectural arrangement that reduces complexity
2Measurement precision
If a conventional fractional-N PLL uses a multi-modulus divider, then frequency switching resolution is enhanced, but switching time increases
Solution Approach 1:
The patent employs a dynamic overflow signal generated by the delta-sigma modulator that continuously adjusts the phase detection based on accumulated fractional frequency requirements. This dynamic mechanism enables fast frequency switching by avoiding the need to reconfigure divider ratios, as the fixed integer divider maintains constant operation while the overflow signal provides the necessary frequency resolution adjustments
Solution Approach 2:
The delta-sigma modulator performs preliminary accumulation of fractional frequency requirements before they manifest as output frequency changes. By pre-calculating and accumulating the necessary phase adjustments in the feedback path, the system prepares frequency transitions in advance, enabling faster switching without sacrificing resolution
3Device complexity
If a simplified fractional-N PLL eliminates the multi-modulus divider, then device complexity is reduced, but maintaining frequency division ratio becomes challenging
Solution Approach 1:
The patent employs a feedback mechanism where the delta-sigma modulator receives the divided feedback signal from the integer divider and generates an overflow signal that feeds back to the phase frequency detector. This feedback loop continuously monitors and adjusts the phase detection based on accumulated fractional frequency requirements, ensuring accurate frequency division ratios are maintained despite the elimination of the multi-modulus divider
Solution Approach 2:
The overflow signal from the delta-sigma modulator acts as an intermediary that bridges the gap between the fixed integer divider and the required fractional frequency synthesis. This intermediate signal carries the accumulated fractional frequency information and modulates the phase detection accordingly, enabling the system to achieve accurate frequency division ratios without directly controlling a variable divider
Data Source
AI summary
A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).