Fractional-N PLL Divider Compensation for Reference Spur Reduction
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Solution Overview
Problem
Phase lock loops (PLLs) face issues with high-reference spurs and increased phase noise due to non-50% duty cycle reference clocks, which cause mismatches in even and odd clock periods, leading to uncorrelated noise and in-band noise increases.
Innovation Solution
A method that determines the phase difference between even and odd cycles of a reference clock and adjusts the division value used by a divider to generate the feedback clock, applying delta values of alternating polarity to align the feedback clock with the reference clock, thereby reducing noise and tracking temperature variations without altering the reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a reference clock doubler circuit is used to double the reference clock frequency, then the reference clock frequency is doubled, but the non-50% duty cycle causes mismatch between even and odd clock periods, generating high-reference spurs and increasing phase noise
Solution Approach 1:
The patent segments the reference clock period into even and odd cycles, treating them separately with different division values. This allows independent compensation for each half-cycle, addressing the root cause of the mismatch that generates spurs and noise.
Solution Approach 2:
The patent dynamically adjusts the division value based on whether the current cycle is even or odd. The divider switches between different division values (N_even and N_odd) to compensate for the duty cycle mismatch, making the system adaptive rather than static.
2Manufacturing precision
If digital tuning is used to adjust the duty cycle of the reference clock, then the duty cycle mismatch is corrected, but large glitches are introduced to the output clock
Solution Approach 1:
The patent introduces an intermediary compensation mechanism at the divider stage rather than directly modifying the reference clock. The divider acts as a mediator that absorbs the duty cycle mismatch through alternating division values, preventing glitches from propagating to the output clock.
3Manufacturing precision
If analog tuning is used to adjust the duty cycle of the reference clock, then the duty cycle mismatch is corrected, but analog noise is introduced
Solution Approach 1:
The patent replaces the analog tuning mechanism with a digital solution. Instead of using analog circuits to adjust duty cycle, the system uses digital division values (N_even and N_odd) controlled by a phase difference detector, eliminating analog noise while maintaining precision.
4Measurement precision
If the division value is adjusted to compensate for phase difference, then the feedback clock alignment is improved, but the system complexity increases
Solution Approach 1:
The patent implements a feedback loop where the phase difference detector continuously monitors the alignment between reference and feedback clocks and adjusts the division values accordingly. This closed-loop feedback mechanism automatically maintains precise alignment without requiring complex manual calibration.
Data Source
AI summary
In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.