Fractional-N PLL Divider Compensation for Reference Clock Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fractional-N phase locked loops (PLLs) face noise issues due to unequal successive time periods in the reference clock, leading to increased output clock jitter and reference spurs, which existing technologies have not effectively addressed.
Innovation Solution
A feedback divider block with a division circuitry and a division factor generator that includes a splitter and a delta-sigma modulator core, which generates a sequence of divisor values to compensate for the unequal time periods, using a compensation factor to adjust the division factor and reduce noise contributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency doubling or other techniques are used to generate reference clock from asymmetric source clock, then the reference clock frequency can be generated, but unequal successive time periods are introduced causing noise and jitter in output clock
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector detects phase errors between reference clock and feedback clock, and the division factor generator uses this information to dynamically adjust divisor values. This closed-loop feedback system compensates for the unequal time periods introduced by frequency doubling, thereby reducing output clock jitter and noise while maintaining the desired reference clock frequency.
Solution Approach 2:
The patent dynamically changes the division factor (parameter) based on detected phase errors. By adjusting the divisor values in the feedback divider block according to the phase error magnitude and direction, the system compensates for the asymmetric time periods in the reference clock, eliminating noise and jitter in the output clock.
2Device complexity
If conventional phase locked loop is used without compensation, then the circuit is simpler, but noise and spurs are introduced in the output clock due to unequal reference clock periods
Solution Approach 1:
The patent introduces a feedback path from the phase detector output to the division factor generator. This feedback mechanism enables real-time detection and compensation of phase errors caused by unequal reference clock periods, effectively reducing reference spurs and noise without requiring major structural changes to the PLL architecture.
Solution Approach 2:
The patent performs preliminary compensation by adjusting the division factor before the feedback clock is generated. The division factor generator pre-calculates and applies correction values based on phase error detection, preventing noise and spurs from being introduced into the output clock in the first place.
3Device complexity
If division factor is kept constant, then the divider operation is simpler, but it cannot compensate for varying phase errors due to asymmetric reference clock
Solution Approach 1:
The patent transforms the static division factor into a dynamic parameter that varies in response to phase errors. The division factor generator continuously updates the divisor values based on real-time phase error feedback, enabling the divider operation to adapt and compensate for the asymmetric characteristics of the reference clock, thereby improving phase alignment accuracy.
Solution Approach 2:
The patent changes the division factor parameter dynamically based on detected phase errors. By modulating the divisor values according to the magnitude and direction of phase misalignment, the system achieves precise compensation for asymmetric reference clock periods while maintaining relatively simple divider circuitry.
Data Source
AI summary
A division factor generator of a feedback divider block in a fractional-N phase locked loop (PLL). The division factor generator is enabled to operate with larger values of division factors without increased complexity of an internal modulator core implemented, for example, as a delta-sigma modulator (DSM) having a signal transfer function (STF), wherein the STF always generates only an integer value as an output in response to an integer value received as input.