Fractional Analog PLL Without Feedback Divider for Low-Power Locking
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Solution Overview
Problem
Conventional phase-locked loop circuits in wireless devices consume significant power, especially in listen or sniff modes, due to the operation of an open-loop to avoid the power consumed in the feedback divider, and the residual frequency error and phase noise, which limits their usability in high-frequency wireless communications.
Innovation Solution
The solution involves disabling the feedback divider circuit in the PLL and using a re-timer to derive phase information from the VCO, combined with sigma-delta modulation to achieve fractional N synthesis, allowing the PLL to operate efficiently with reduced power consumption and improved frequency accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the feedback divider circuit is enabled in the PLL, then frequency control accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts the essential function of the feedback divider (frequency division) and implements it through a different architectural approach using a re-timer circuit that derives phase information directly from the VCO output without requiring a traditional feedback divider. This eliminates the power-consuming feedback divider while maintaining frequency control capability through phase comparison of the re-timed signal with the reference signal.
2Measurement precision
If the PLL is kept running during listen or sniff mode, then frequency accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming feedback divider circuit from the PLL architecture, enabling the PLL to maintain accurate frequency control during listen or sniff modes with significantly reduced power consumption. The re-timer-based phase information derivation provides sufficient frequency accuracy for these low-power operational modes.
3Use of energy by moving object
If the VCO runs in open-loop to avoid feedback divider power consumption, then power consumption is reduced, but residual frequency error and phase noise increase
Solution Approach 1:
The patent introduces a re-timer circuit as an intermediary between the VCO output and the phase frequency detector. The re-timer derives phase information from the VCO output signal and provides it to the PFD for comparison with the reference signal. This intermediary enables closed-loop frequency control without requiring a traditional feedback divider, thus maintaining frequency accuracy while avoiding the power consumption penalty.
Data Source
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Figure 2A
Figure 2b
AI summary
An integrated circuit device [200] is provided. In some examples, the integrated circuit device [200] includes a first re-timer [216] configured to receive a reference clock signal [201] and a voltage controlled oscillator (VCO) output signal [212], and the first re-timer [216] is configured to provide a first re-timed clock signal [216 A] in response to the reference clock signal [201] and the VCO output signal [212], A multiplexer [215] receives the first re-timed clock signal [216 A] and provides a feedback clock signal [215A], A phase frequency detector [202] receives the feedback clock signal [215 A] and the reference clock signal [201] and provides an error signal [202A and 202B] in response to the feedback clock signal [215 A] and the reference clock signal [201], A VCO [211] receives a voltage signal [220A] based on the error signal [202 A and 202B], and the VCO [211] is configured to provide the VCO output signal [212] in response to the voltage signal [220 A].