Fractional-N PLL Quantization Error Compensation With Fewer Edge Conversions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional fractional-N phase-locked loop circuits face issues with high power consumption and phase noise due to frequent edge conversions and quantization errors during fractional frequency division.
Innovation Solution
A low-power fractional-N phase-locked loop circuit design that combines edge conversion processes in quantization error compensation and sampling phase detection, using a phase detector with a voltage-to-current converter and digital logic processor to directly adjust capacitance or current for error compensation, reducing the number of edge conversions and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital-to-time converter is inserted into the feedback loop or reference path to compensate quantization error, then quantization phase error is compensated, but power consumption increases and phase noise degrades
Solution Approach 1:
The patent combines the quantization error compensation function and phase detection function into a single phase detector module. The phase detector directly compensates for quantization phase errors by adjusting its internal operation based on the fractional frequency division ratio, eliminating the need for a separate digital-to-time converter. This integration reduces the number of edge conversions and associated power consumption while maintaining effective quantization error compensation.
Solution Approach 2:
The patent extracts the quantization error compensation function from the traditional digital-to-time converter and implements it directly within the phase detector. By taking out the compensation operation from a separate conversion stage and embedding it in the phase detection process, the system achieves error compensation with fewer edge conversions and reduced power consumption.
2Measurement precision
If multiple edge conversions are performed in digital-to-time converter and sampling phase detector, then quantization error is compensated and phase detection is performed, but power consumption increases
Solution Approach 1:
The patent merges the edge conversion operations of the digital-to-time converter and sampling phase detector into a single edge conversion process within the integrated phase detector. By combining these functions, the system performs both quantization error compensation and phase detection with only one edge conversion per measurement cycle, significantly reducing power consumption while maintaining detection accuracy.
Solution Approach 2:
The patent implements continuous phase detection and error compensation within a unified feedback loop, where the phase detector continuously monitors phase errors and adjusts frequency division ratios in real-time. This continuous operation eliminates the need for separate conversion stages and maintains accurate phase detection with reduced power consumption through optimized switching operations.
3Manufacturing precision
If fractional frequency division is used to achieve frequency synthesis, then frequency resolution is improved, but quantization noise is introduced
Solution Approach 1:
The patent employs a feedback mechanism where the phase detector continuously monitors the phase error between the reference signal and the frequency-divided signal, and uses this information to dynamically adjust the frequency division ratio. The feedback loop compensates for quantization noise by correcting phase errors in real-time, allowing the system to maintain high frequency resolution while minimizing the harmful effects of quantization noise through continuous error correction.
Data Source
AI summary
Disclosed is a low-power fractional-N phase-locked loop circuit, which comprises a phase detector, a voltage-to-current converter, a loop filter, a voltage-controlled oscillator, a frequency divider and a digital logic processor; the phase detector, the voltage-to-current converter, the loop filter, the voltage-controlled oscillator and the frequency divider are connected in sequence; a reference signal is input from the phase detector, the phase detector detects the phases of the reference signal and a feedback signal with a quantization error output by the frequency divider, compensates a quantization phase error generated by fractional frequency division, and outputs a compensated phase detection result to the voltage-to-current converter; the quantization error generated by fractional frequency division is converted into a voltage domain through a digital domain or directly coupled to a phase error signal in the phase detector to complete the compensation of the quantization error.