PI-Based Fractional-N PLL Sampling for Quantization Error Cancellation
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) in RF transmitters or receivers face significant phase noise degradation and quantization errors due to the modulation of the integer divisor N, which existing solutions like digital-to-time converters and phase interpolators struggle to fully mitigate, especially across wide dynamic ranges.
Innovation Solution
Incorporating a phase interpolation-based sampler and a fractional frequency divider circuit that adjusts slope signals based on quantization error corrections, allowing for effective cancellation of quantization errors and improved phase noise performance by dynamically adjusting the RC time constants in the PLL feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the integer divisor N is modulated among two or more integers using a delta-sigma modulator to generate fractional frequencies, then a greater number of frequencies within a frequency band can be generated, but quantization error is introduced that degrades phase noise performance
Solution Approach 1:
The patent implements a feedback mechanism where the fractional frequency divider circuit generates a quantization error correction indication that is fed back to adjust the slope signal. This closed-loop feedback allows the system to detect and correct quantization errors introduced by N modulation, thereby maintaining phase noise performance while enabling fractional frequency generation.
Solution Approach 2:
The patent introduces a phase interpolation-based sampler as an intermediary component between the PFD and the loop filter. This sampler includes RC circuitry that generates slope signals, which can be dynamically adjusted based on quantization error correction indications. The intermediary sampler acts as a buffer that can compensate for quantization errors without disrupting the overall frequency synthesis operation.
2Reliability
If a digital-to-time converter is included in the reference signal path to cancel quantization error, then quantization error can be reduced, but phase noise is introduced by the DTC especially when covering a wide dynamic range
Solution Approach 1:
Instead of using a DTC to copy and adjust the reference clock signal (which introduces phase noise), the patent implements quantization error correction directly in the feedback path. The fractional frequency divider circuit generates a quantization error correction indication that adjusts the slope signal, effectively copying the error correction function without requiring signal path manipulation that introduces phase noise.
3Adaptability or versatility
If a phase interpolator is included in the feedback path to relax the DTC's dynamic range requirement, then DTC phase noise performance can be improved, but significant phase noise degradation remains
Solution Approach 1:
The patent extracts the quantization error correction function from the reference signal path (where DTC would be needed) and places it directly in the feedback path. By taking out the error correction operation and applying it directly to the slope signal based on quantization error correction indications, the system eliminates the need for DTC and phase interpolator components that would otherwise be required, thereby avoiding their associated phase noise issues.
4Adaptability or versatility
If the value of N is adjusted to generate more frequencies within a frequency band, then frequency versatility is improved, but the PLL becomes more susceptible to quantization errors
Solution Approach 1:
The patent uses feedback from the fractional frequency divider circuit to detect quantization errors and generate correction indications. This feedback mechanism allows the system to maintain frequency accuracy even when N is frequently adjusted to generate different frequencies within the band. The correction indication dynamically adjusts the slope signal to compensate for quantization errors, preserving measurement precision.
Data Source
AI summary
A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.