Fractional-N PLL Feedback Clock Selection for Lower Quantization Error
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Solution Overview
Problem
Phase-locked loops (PLLs) with fractional-N frequency synthesis face challenges in reducing quantization error (QE), which degrades performance by increasing in-band phase noise and requiring larger digital-to-time converter (DTC) ranges, making it difficult to design efficient DTCs with low integral nonlinearity and thermal noise.
Innovation Solution
The solution involves modifying the multi-modulus divider (MMDIV) to generate two feedback clocks based on differential VCO inputs and a selection control signal, allowing the PLL to select one clock for phase detection, effectively reducing the quantization error by half, thereby reducing the required DTC range and thermal noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-order sigma-delta modulator is used to reduce fractional spurs, then fractional spur levels are improved, but quantization error increases rapidly
Solution Approach 1:
The feedback clock path is segmented into two separate paths, each processing one differential input signal (VCO_P and VCO_N) independently through separate flip-flops. This segmentation allows the quantization error to be distributed and reduced across multiple paths rather than concentrated in a single path.
Solution Approach 2:
Instead of using a single feedback clock path, the invention inverts the conventional approach by creating two symmetric feedback paths that process inverted differential signals. The two paths are then combined through a multiplexer, effectively canceling out quantization error through the inverted signal paths.
2Reliability
If a digital-to-time converter with larger delay range is used to cover the entire QE range, then QE cancellation is improved, but DTC thermal noise increases proportionally to the square of the delay
Solution Approach 1:
The single large-range DTC is segmented into two smaller-range DTCs, each handling one differential path. This reduces the delay range requirement for each DTC by half, and since thermal noise increases with the square of delay, the thermal noise is reduced by approximately a factor of four compared to a single large-range DTC.
Solution Approach 2:
The invention transitions from a single-dimensional DTC design (one delay range) to a two-dimensional differential architecture where two DTCs operate in parallel with reduced delay ranges. This dimensional expansion allows the system to achieve the same QE cancellation performance with reduced individual component specifications.
3Reliability
If a high performance PD is used to handle large QE, then QE impact on PLL performance is improved, but charge pump and TDC design becomes challenging
Solution Approach 1:
The single PD handling large QE is segmented into two PDs operating in parallel, each processing one differential path with reduced QE. This segmentation reduces the QE burden on each individual PD, allowing the use of simpler, more reliable PD designs without requiring high-performance components capable of handling large quantization errors.
Data Source
AI summary
Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.