Fractional PLL Digital Control Using Higher-Frequency Sampling
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Solution Overview
Problem
Fractional phase locked loops (PLLs) face significant jitter due to quantization noise introduced by the digital control circuit for controlling the fractional frequency divider in the feedback loop, which affects the accuracy of clock and data recovery in data transmission systems.
Innovation Solution
The implementation of a digital control circuit driven by a sampling clock with a frequency higher than the feedback clock, which reduces quantization noise and separates it further from the PLL output clock, thereby reducing jitter and improving the operational stability of digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digital control circuit is used to control the fractional frequency divider in the feedback loop, then the PLL can achieve fractional frequency division, but quantization noise is introduced which increases jitter in the output clock
Solution Approach 1:
The patent introduces an intermediary frequency multiplier that converts the feedback clock at frequency F to a higher frequency sampling clock (multiple of F). This intermediary signal allows the digital control circuit to operate at a higher frequency, thereby reducing quantization noise and jitter in the output clock while maintaining fractional frequency division capability.
Solution Approach 2:
The patent changes the operating parameter (frequency) of the digital control circuit by using a frequency multiplier. The sampling clock frequency is changed from F to a higher frequency (multiple of F), which reduces quantization noise and improves output clock quality while preserving the fractional division function.
2Device complexity
If the digital control circuit operates at the feedback clock frequency, then the circuit complexity is minimized, but quantization noise affects the fundamental frequency of the PLL output clock
Solution Approach 1:
The frequency multiplier acts as an intermediary that enables the digital control circuit to operate at a higher frequency without directly complicating the feedback path. The mediator allows precise phase detection by ensuring the sampling clock frequency is a multiple of the feedback clock frequency, preventing quantization noise at the fundamental frequency.
Solution Approach 2:
The patent moves the quantization noise to a different frequency dimension by using a higher frequency sampling clock. The noise is shifted from the fundamental frequency F to higher frequency components (multiples of F), effectively separating it from the fundamental PLL output clock frequency.
3Reliability
If a frequency multiplier is added to generate a higher frequency sampling clock, then quantization noise is reduced, but the device complexity increases
Solution Approach 1:
The frequency multiplier is designed to provide multiple functions: it generates the higher frequency sampling clock for the digital control circuit, ensures the sampling frequency is a multiple of the feedback clock frequency, and prevents quantization noise at the fundamental frequency. This multi-functionality justifies the added component.
Solution Approach 2:
The patent uses feedback from the PLL output clock through the frequency divider to generate the sampling clock. This feedback mechanism ensures the sampling clock frequency is always a multiple of the feedback clock frequency, automatically adapting to different operating conditions while reducing quantization noise.
Data Source
AI summary
A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.