Dynamic Fractional PLL Divider for Jitter and Spur Attenuation
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Solution Overview
Problem
Conventional Phase-Locked Loop (PLL) frequency synthesizers face challenges in attenuating noise spurs and jitters in output signals due to their low-bandwidth nature and complex circuitry requirements, particularly in analog implementations and challenging design linearity in digital PLLs.
Innovation Solution
A dynamic fractional divider is introduced in the feedback loop of the PLL, with a dynamically adjustable divide ratio that responds to phase differences between input and output signals, using a sigma delta modulator and modulus divider to generate a feedback signal that adjusts the output frequency, thereby reducing jitter accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional low-bandwidth jitter attenuator is used, then jitter performance is improved, but circuit complexity and silicon area increase
Solution Approach 1:
The patent implements a dynamic divide ratio mechanism that adjusts the feedback divider ratio in real-time based on detected phase errors and jitter conditions. This dynamic adjustment allows the PLL to adaptively attenuate jitter without requiring a fixed low-bandwidth filter, thereby reducing circuit complexity while maintaining jitter performance.
Solution Approach 2:
The patent changes the divide ratio parameter dynamically during operation. By modulating the divide ratio based on the phase difference between reference and feedback signals, the system achieves jitter attenuation through parameter variation rather than through complex analog filtering circuitry.
2Reliability
If an analog PLL is used to address jitter performance, then jitter attenuation is achieved, but circuit complexity and cost increase
Solution Approach 1:
The patent replaces complex analog jitter attenuation circuitry with a digital control mechanism. The dynamic divide ratio is controlled through digital logic that processes phase error signals, substituting analog filtering components with a digitally-controlled feedback divider that achieves similar jitter attenuation effects with simpler circuitry.
3Device complexity
If a digital PLL is used to address jitter, then circuit complexity is reduced, but design linearity specifications become more challenging
Solution Approach 1:
The patent employs dynamic divide ratio adjustment that continuously adapts to phase error conditions. This dynamic behavior allows the digital PLL to maintain linear operation across varying conditions by adjusting the feedback division in real-time, thereby simplifying linearity requirements compared to static digital PLL designs.
4Device complexity
If a static divide ratio is used in the feedback loop, then circuit simplicity is maintained, but jitter and noise spurs are not attenuated
Solution Approach 1:
The patent transitions from a static divide ratio to a dynamically changing divide ratio. The divide ratio is adjusted based on the phase difference between reference and feedback signals, enabling jitter attenuation while maintaining relatively simple circuit architecture through parameter modulation rather than structural complexity.
Data Source
AI summary
Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.