Fractional-N PLL Filtering for Quantization Noise and Bandwidth
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Solution Overview
Problem
Fractional-N phase-locked loops face a tradeoff between widening bandwidth and suppressing quantization noise, with existing designs compromising on stability and spectral performance in applications like wireless communications.
Innovation Solution
A fractional-N phase-locked loop design incorporating a digital finite impulse response filter to split the output into integer and fractional parts, processed through separate paths with adjustable delay lines and phase detectors, and combined as a weighted sum, along with dynamic element matching to compensate for mismatches, effectively decoupling bandwidth and noise suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If quantization noise suppression is implemented in a fractional-N phase-locked loop, then spectral performance is improved, but bandwidth is reduced
Solution Approach 1:
The patent segments the feedback path into two separate paths: a first path for processing the integer part of the division ratio and a second path for processing the fractional part. This segmentation allows independent optimization of each path, enabling noise suppression in the fractional path while maintaining bandwidth through the integer path, thereby resolving the contradiction between noise suppression and bandwidth.
Solution Approach 2:
The patent introduces an intermediary structure with two separate phase detectors (first and second phase detectors) that process signals from the reference input and feedback paths respectively. This intermediary architecture enables the system to handle integer and fractional division components separately, allowing bandwidth preservation through the integer path while suppressing quantization noise through the fractional path.
2Device complexity
If a single path is used for frequency division, then device complexity is reduced, but frequency agility is limited
Solution Approach 1:
The feedback path is segmented into two independent paths with separate phase detectors and processing circuits. This segmentation enables the system to achieve high frequency agility by independently adjusting integer and fractional division ratios while maintaining manageable circuit complexity through modular architecture, where each path can be optimized separately.
Solution Approach 2:
The patent implements dynamic element matching (DEM) techniques that dynamically adjust and compensate for mismatches between circuit elements in real-time. This dynamic compensation mechanism maintains high frequency agility across varying operating conditions while keeping the overall device complexity controlled through adaptive rather than static design approaches.
Data Source
AI summary
This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.