Fractional-N PLL Noise Cancelation for Quantization Jitter
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Solution Overview
Problem
Fractional-N phase lock loop (PLL) circuits face challenges in effectively canceling quantization noise, which is injected by the Delta-Sigma modulator and passes through the programmable divider, phase-frequency detector, and charge pump circuits, limiting high-bandwidth applications.
Innovation Solution
A noise cancelation circuit is introduced, comprising a synchronization circuit to generate synchronized feedback clock signals, a phase-frequency detector to produce control signals with differing pulse widths, and a current digital-to-analog converter to apply noise canceling currents, effectively canceling quantization noise by matching the cancelation charge with the noise source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fractional-N PLL circuit uses a Delta-Sigma modulator to achieve high bandwidth operation, then the PLL can operate at higher bandwidths, but quantization noise is injected into the feedback path limiting performance
Solution Approach 1:
The patent converts the harmful quantization noise generated by the Delta-Sigma modulator into a beneficial signal by generating a compensating signal that mirrors the noise characteristics. The noise cancelation circuit uses the same modulator output to create an equal and opposite noise signal, effectively transforming the harmful quantization noise into a useful cancelation mechanism that allows high-bandwidth operation without noise degradation
2Object-generated harmful factors
If noise cancelation current is applied to cancel quantization noise, then quantization noise is reduced, but additional circuit complexity is introduced
Solution Approach 1:
The patent merges the noise cancelation function with the existing charge pump circuitry by integrating the noise cancelation current paths into the standard PLL charge pump structure. The same PFD outputs control both the normal charge pump operation and the noise cancelation current sources/sinks, combining multiple functions into a unified circuit architecture that reduces overall complexity despite adding noise cancelation capability
Data Source
AI summary
A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.