Fractional-N PLL Feedback for Deterministic Phase Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In phase-locked loop circuits, the variability in the pattern of the division ratio control signal output from a ΔΣ modulator leads to differing phases of the output signal across multiple circuits with the same configuration, causing malfunctions in communication apparatus due to phase differences.
Innovation Solution
A phase-locked loop circuit design that includes a division ratio control circuit, quantization error detection circuits, and a negative feedback signal generating circuit to synchronize the division ratio control signal, ensuring that the output signal of one phase-locked loop circuit aligns with another having the same configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a ΔΣ modulator is used to implement fractional division by randomly modulating the division ratio, then frequency resolution is improved, but phase consistency deteriorates because the pattern of the division ratio control signal varies even with the same input signal
Solution Approach 1:
The patent introduces a feedback mechanism where the division ratio control signal pattern is detected and fed back to control the ΔΣ modulator. This feedback loop ensures that the same input signal always produces the same division ratio control signal pattern, thereby maintaining phase consistency across multiple phase-locked loop circuits while preserving the frequency resolution benefits of ΔΣ modulation.
Solution Approach 2:
The patent changes the operational parameters of the ΔΣ modulator by introducing control signals that regulate the division ratio modulation pattern. By adjusting these parameters through feedback control, the system maintains deterministic behavior (same input → same pattern) while preserving the fractional division capability that provides high frequency resolution.
2Reliability
If the pattern of the division ratio control signal is controlled to ensure phase consistency, then phase consistency is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The system uses the existing quantization error detection capability of the ΔΣ modulator to generate the feedback signal. The quantization error, which is already being calculated for fractional division, is repurposed to control the division ratio control signal pattern. This self-service approach achieves phase consistency without requiring completely separate control circuits, thereby limiting the increase in device complexity.
Solution Approach 2:
The feedback signal generating circuit performs multiple functions: it detects the quantization error for fractional division control and simultaneously generates the control signal for deterministic division ratio patterning. This multi-functionality reduces the need for separate dedicated circuits, thereby managing device complexity while achieving phase consistency.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A phase-locked loop circuit includes: a division ratio control circuit (8) controlling a division ratio of an output signal of a variable frequency divider (7) on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider (7); a first phase detection circuit (10) calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit (3); a second phase detection circuit (13) calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit (8) controls the division ratio of the output signal of the variable frequency divider (7) in synchronization with the reference signal; and a shift circuit (17) generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the generated negative feedback signal and the division ratio setting signal to the division ratio control circuit (8).