Fractional-N PLL Spread Spectrum Logic for Phase Step Conflicts
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Solution Overview
Problem
The integration of spread spectrum clocking (SSC) and fractional-N phase locked loop (PLL) circuits in digital systems often leads to conflicts when both request phase steps simultaneously, either in the same or opposite directions, which can cause phase divider failures and complicate phase shifting, making it difficult to effectively counteract electromagnetic interference (EMI).
Innovation Solution
A combined spread spectrum and fractional-N phase locked loop circuit is designed with a logic interface circuit that combines directional and phase step control signals from both SSC and fractional-N logic circuits, ensuring that phase steps are managed to avoid conflicts, either by performing phase steps in successive cycles or omitting them when necessary, thus preventing huge phase steps and maintaining the center frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both spread spectrum logic and fractional-N logic request phase steps simultaneously in the same direction, then the phase selector must handle double the phase steps, but this causes huge phase steps that can make the feedback divider fail
Solution Approach 1:
The logic interface circuit performs preliminary detection of simultaneous phase step requests from spread spectrum and fractional-N logic, and preemptively schedules them in successive feedback clock periods rather than allowing them to occur simultaneously, thereby preventing huge phase steps that would cause feedback divider failure
Solution Approach 2:
The logic interface circuit acts as an intermediary between the spread spectrum logic and fractional-N logic, mediating their conflicting phase step requests by serializing them in time, thus protecting the phase selector and feedback divider from overwhelming simultaneous demands
2Ease of operation
If both spread spectrum logic and fractional-N logic request phase steps simultaneously in opposite directions, then phase steps cancel out, but this creates timing conflicts and uncertainty in phase control
Solution Approach 1:
The logic interface circuit uses feedback from detecting simultaneous opposite-direction phase step requests to determine when to suppress phase step generation, ensuring that conflicting requests are resolved by omitting the phase step in that clock period, thereby maintaining phase control reliability
Solution Approach 2:
The logic interface circuit applies preliminary anti-action by detecting and suppressing contradictory phase step requests before they can cause timing conflicts, using the detection of simultaneous opposite-direction requests to prevent the harmful timing uncertainty
3Object-affected harmful factors
If electromagnetic shielding is used to counteract EMI, then EMI protection is improved, but hardware cost and complexity increase considerably
Solution Approach 1:
The spread spectrum logic modulates the center frequency by adding phase steps to the feedback signal, spreading the spectral energy and reducing EMI without requiring any physical shielding hardware, thus achieving EMI protection through parameter modification rather than structural additions
Solution Approach 2:
The patent replaces the mechanical/electrical approach of electromagnetic shielding with a signal processing approach using spread spectrum clocking, substituting physical barrier methods with frequency modulation techniques to achieve the same EMI mitigation goal
Data Source
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AI summary
A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase- frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal. A logic interface circuit combines the directional control output signal from the spread spectrum logic circuitry, the phase step control signal from the spread spectrum logic circuitry, and the phase step control signal from the fractional logic circuitry. This means that when both of the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in thesame direction, a single phase step control signal is passed to the phase selector and a further phase step control signal is passed to the phase selector in a subsequent clock period. Further, when the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in opposite directions, no phase step control signal is passed to the phase selector.