Fractional PLL Synthesizer Phase Control via Load Enable Timing
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Solution Overview
Problem
Conventional frequency synthesizers face difficulties in synchronizing phase difference control with reference signals and require complex structures due to low-speed clock, data, and load enable signals, as well as needing external frequency and phase setting data for parallel operation.
Innovation Solution
A frequency synthesizer with multiple clock, data, and load enable signal generating circuits synchronized with a reference signal, shift register circuits for PLL setting data output, and fractional modulators for generating dividing number control data, which controls the timing of load enable signals to manage phase differences between high-frequency signals from multiple fractional PLL synthesizers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional low-speed clock, data, and load enable signals are used in frequency synthesizers, then the basic operation is simplified, but phase difference control synchronized with reference signals becomes difficult to achieve
Solution Approach 1:
The patent applies dynamics by making the load enable signal timing adjustable and synchronized with the reference signal. The load enable signal generating circuit dynamically adjusts the timing of load enable signals based on phase difference settings, allowing phase control while maintaining signal generation simplicity. This resolves the contradiction by introducing dynamic timing adjustment capability without fundamentally changing the basic signal generation architecture.
2Adaptability or versatility
If parallel operation of multiple fractional PLL synthesizers is implemented, then frequency coverage and signal generation capability are improved, but the structure becomes more complex due to separate frequency and phase setting data inputs
Solution Approach 1:
The patent merges the frequency setting data and phase difference setting data into a single integrated control structure. The fractional modulators receive both types of setting data through unified control circuits, eliminating the need for separate external inputs for frequency and phase control. This combining approach enables parallel operation of multiple fractional PLL synthesizers while simplifying the overall control structure.
Solution Approach 2:
The control circuit is designed with multi-functionality to handle both frequency setting and phase difference setting operations. The same control circuit generates both frequency setting data and phase difference setting data for the parallel-operating fractional PLL synthesizers, making the control structure universal rather than requiring separate dedicated circuits for each function.
3Adaptability or versatility
If phase difference control is implemented by external frequency and phase setting data inputs, then control flexibility is maintained, but the synthesizer requires more complex external connections and control interfaces
Solution Approach 1:
The frequency synthesizer implements self-service by internally generating both frequency setting data and phase difference setting data through its own control circuits. The synthesizer does not require complex external inputs for separate frequency and phase control, as these are generated internally based on unified control signals. This reduces external interface complexity while maintaining control flexibility through internal data generation and processing.
Data Source
AI summary
Disclosed is a frequency synthesizer including first and second shift register circuits 3a and 3b each for outputting PLL setting data on a rising edge of a load enable signal, first and second fractional modulators 4a and 4b each for generating dividing number control data on the basis of the PLL setting data in synchronization with a reference signal, and first and second fractional PLL synthesizers 5a and 5b each for generating a high frequency signal according to the PLL setting data, the reference signal, and the dividing number control data. By controlling the timing of the load enable signal, the frequency synthesizer carries out phase control between the high frequency signals generated by the first and second fractional PLL synthesizers 5a and 5b.