Fractional-N PLL Delayed Feedback for Jitter and Phase Error Control
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Solution Overview
Problem
Fractional-N PLLs in integrated circuits suffer from quantization noise due to switching between integer multipliers, leading to phase errors and jitter in the output clock signal, which existing technologies have not adequately addressed.
Innovation Solution
A clock generation unit comprising an oscillator circuit, a frequency divider circuit, and a delay circuit that generates a clock signal as a non-integer multiple of a reference signal, using a feedback signal and an adjustment factor to select and modify delayed feedback signals, thereby compensating for quantization errors and reducing jitter through calibration algorithms like binary and sequential search.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N PLL switches between integer divisor values to generate a fractional multiple frequency, then the target frequency is achieved, but quantization noise is introduced in the output clock signal
Solution Approach 1:
The feedback divisor is segmented into multiple sub-dividers that can be independently controlled. By dividing the feedback path into stages with adjustable divisors, the system achieves fine-grained frequency control without quantization noise, as each stage contributes a portion of the total division ratio rather than requiring abrupt switching between discrete values
Solution Approach 2:
The feedback divisor values are made dynamic and continuously adjustable rather than fixed or abruptly switched. The system employs continuous frequency tuning mechanisms that allow the divisor to vary smoothly, eliminating the quantization effects that arise from discrete switching between integer values
2Adaptability or versatility
If the divisor value is changed to adjust the output frequency, then frequency programmability is achieved, but phase errors and jitter are introduced
Solution Approach 1:
The system incorporates a feedback mechanism that continuously monitors the output frequency and phase, then adjusts the divisor values to compensate for errors. This closed-loop control ensures that frequency programming does not compromise phase accuracy, as the feedback loop corrects deviations in real-time
Solution Approach 2:
The system performs preliminary calibration and adjustment of the divisor values before operation to establish optimal settings that minimize phase errors. By pre-configuring the feedback path divisors based on the desired output frequency, the system avoids introducing phase inaccuracies during dynamic operation
Data Source
AI summary
A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.