Fractional-N PLL Phase Prediction for Low-Power Clock Locking
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Solution Overview
Problem
Existing fractional-N PLLs face challenges in achieving low power consumption while maintaining high accuracy and low jitter, as they often require significant energy to operate effectively.
Innovation Solution
The implementation of a modulo-K counter and a fractional phase predictor that calculates a predicted phase based on a rational frequency control word, with a loop filter used to correct the controlled oscillator's frequency, allowing for efficient phase locking and reduced power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing fractional-N PLLs are used to achieve high accuracy and low jitter, then the output clock frequency resolution is improved, but the power consumption increases significantly
Solution Approach 1:
The PLL is divided into two separate loops: a primary integer-N PLL that consumes less power and a secondary fractional-N PLL that provides high accuracy. By segmenting the functionality across two loops with different power characteristics, the system achieves high frequency resolution while managing power consumption through selective operation of each loop based on application requirements
Solution Approach 2:
The system dynamically changes operational parameters by switching between integer-N and fractional-N modes, or between single-loop and dual-loop configurations. This allows the PLL to adapt its power consumption and accuracy characteristics to match the specific requirements of different operating conditions, achieving optimal balance between power and precision
2Adaptability or versatility
If a single feedback loop PLL is used, then the device complexity is reduced, but the capability to switch between multiple reference clock signals is lost
Solution Approach 1:
The PLL system is designed with multi-functionality to handle both single and multiple reference clock signals. The architecture can operate as a single-loop PLL for simple applications or expand to a dual-loop configuration for applications requiring switching between multiple reference clocks, making the system universally applicable across different scenarios without requiring complete redesign
Solution Approach 2:
The PLL structure is made dynamic and reconfigurable, allowing it to transition between single-loop and dual-loop modes based on operational requirements. This dynamic adaptability enables the system to optimize its complexity level - using the simpler single-loop mode when sufficient and the more capable dual-loop mode when needed - thereby balancing functionality with device complexity
Data Source
AI summary
A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.