Fractional-N PLL Phase Rotation for Spur-Free Clock Generation
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) suffer from instantaneous phase errors and spectral degradation due to dynamic adjustment of the integer divider value, leading to undesired spur energy in the output clock, which existing delta-sigma modulation techniques can only partially mitigate.
Innovation Solution
The implementation of a PLL system with a retimer unit, rotator unit, and delta-sigma modulator that samples and rotates the divided clock phases to produce a single output phase with a controlled rate of change, allowing for quantization-free sub-integer generation and phase-dithered fractional-N generation, reducing spur energy and achieving zero instantaneous phase error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic adjustment of integer divider value is used to achieve fractional-N values, then frequency synthesis capability is improved, but instantaneous phase errors and spectral degradation occur
Solution Approach 1:
The patent segments the divider value adjustment into separate integer and fractional components. The integer divider remains static while the fractional component is handled through phase rotation of multiple divided clock phases, eliminating the need for dynamic integer adjustment and thus preventing fractional-N spurs while maintaining frequency synthesis capability.
Solution Approach 2:
The patent transitions from adjusting the divider value in the time domain to rotating clock phases in the phase domain. By using K different divided clock phases and selectively rotating through them, the system achieves fractional-N functionality without dynamic divider adjustment, thereby eliminating spectral degradation.
2Object-generated harmful factors
If delta-sigma modulation is used to suppress fractional-N spurs, then spur magnitude is reduced, but complete elimination is not achieved
Solution Approach 1:
The patent extracts and eliminates the root cause of fractional-N spurs by removing the dynamic adjustment mechanism entirely. Instead of attempting to suppress spurs through delta-sigma modulation, the invention uses static integer division combined with phase rotation to achieve clean fractional-N output, completely eliminating spur generation at the source.
3Measurement precision
If multiple divided clock phases are used for fractional-N generation, then frequency resolution is improved, but phase rotation control complexity increases
Solution Approach 1:
The patent employs periodic phase rotation through a phase rotation counter that cycles through K different phase combinations. This periodic action simplifies control logic by using a straightforward counting mechanism rather than complex adaptive algorithms, while still achieving fine frequency resolution through the K-phase structure.
Solution Approach 2:
The phase rotation mechanism serves multiple functions simultaneously: it generates the required fractional frequency division, provides fine frequency resolution, and inherently suppresses spurs through the distributed phase structure. This self-service approach eliminates the need for separate control mechanisms for each function.
Data Source
AI summary
A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.