Fractional-N PLL Synchronization Using Reset Phase Adjustment
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Solution Overview
Problem
Fractional-N synthesizers in electronic systems often fail to synchronize the phase of their output clock signal with a reference clock signal predictably, leading to unpredictable locking to multiple possible phases, which is problematic in applications like frequency hopping wireless communications and multi-PLL systems where a consistent phase relationship is crucial.
Innovation Solution
The implementation of a fractional-N synthesizer with a control circuit that includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit, which generates a phase adjustment signal based on the count of reference clock signal periods and synchronizes the PLL to correct for synchronization phase errors, allowing synchronization during any arbitrary period of the reference clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional-N synthesizer is used to provide finer output frequency adjustment steps, then frequency resolution is improved, but phase synchronization becomes unpredictable and locking to multiple phases occurs
Solution Approach 1:
The patent applies preliminary action by resetting the interpolator to a known initial state before synchronization occurs. This ensures that the phase accumulator starts from a defined point, enabling predictable phase locking. The reset mechanism prepares the system in advance for synchronization by clearing any accumulated phase uncertainty that would otherwise prevent reliable phase alignment with the reference clock.
2Adaptability or versatility
If synchronization is attempted during arbitrary periods of the reference clock signal, then synchronization flexibility is improved, but phase error correction complexity increases
Solution Approach 1:
The patent implements feedback through a phase error detector that continuously monitors the phase difference between the synthesized output clock and the reference clock. This feedback mechanism generates a correction signal that is fed back to the interpolator to adjust the division ratio dynamically. The feedback loop enables the system to automatically correct phase errors regardless of when synchronization is initiated, providing adaptability without requiring complex external control mechanisms.
Solution Approach 2:
The patent uses an intermediary phase error detector and correction mechanism that mediates between the arbitrary synchronization request and the PLL's phase locking requirement. This intermediary component translates the arbitrary timing request into a standardized phase correction sequence, allowing flexible synchronization initiation while maintaining simple, standardized correction logic. The intermediary absorbs the complexity of handling arbitrary timing scenarios.
Data Source
AI summary
Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.