Fractional-N PLL Clock Generation for Plesiochronous Transceivers
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Solution Overview
Problem
Current optical communication systems face challenges in synchronizing data rates from multiple fiber optic lines with slightly different reference frequencies, requiring costly and power-intensive external components for plesiochronous clock generation.
Innovation Solution
Integration of fractional-N phase lock loops within a field programmable gate array (FPGA) for plesiochronous clock generation, utilizing digital frequency mismatch numbers to produce a resultant signal at the transmit frequency, eliminating the need for external components and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external components are used for plesiochronous clock generation, then frequency synchronization is achieved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent combines the fractional-N phase lock loop functionality directly into the FPGA fabric, merging previously separate external clock generation components with the programmable logic device. This integration eliminates the need for external components while maintaining precise frequency synchronization capability through the fractional-N PLL implemented in digital logic.
2Measurement precision
If external components are used for plesiochronous clock generation, then frequency synchronization is achieved, but device complexity increases
Solution Approach 1:
The patent integrates the fractional-N phase lock loop circuitry directly into the FPGA fabric, combining multiple previously separate functions (clock generation, frequency division, phase detection) into a single unified device. This reduces the overall system complexity by eliminating external components and interconnections while maintaining the sophisticated frequency synchronization capability.
3Device complexity
If integer-N phase lock loops are used, then circuit simplicity is maintained, but frequency resolution is insufficient for plesiochronous signals
Solution Approach 1:
The patent transitions from integer-N to fractional-N division ratio in the phase lock loop, changing the fundamental operating parameter from discrete integer values to continuous fractional values. This parameter change enables the circuit to achieve the fine frequency resolution required for plesiochronous signal synchronization (within ±50 ppm) while maintaining implementation through standard digital logic techniques within the FPGA.
Data Source
AI summary
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.