Fractional-N PLL Realignment Using Feedback-Matched Clock Pulses
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Solution Overview
Problem
Traditional realignment techniques in PLL circuits are limited to integer-N mode and damage phase noise when applied to fractional-N mode, as they distort the oscillator period due to using a reference clock-generated realignment clock.
Innovation Solution
A new realignment clock (RLP) is generated with the same period as the feedback dividing clock, duplicating the feedback dividing clock's period to maintain an integer ratio with the oscillator clock, improving phase noise performance in fractional-N mode by using a digital-to-time converter and delayed-locked loop to adjust the oscillator period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional realignment technique using reference clock-generated realignment clock is applied to fractional-N mode, then realignment operation can be performed, but phase noise performance is damaged due to oscillator period distortion
Solution Approach 1:
The patent changes the fundamental parameter of the realignment clock generation method. Instead of generating the realignment clock from the reference clock (traditional method), the invention generates it from the feedback dividing clock. This parameter change ensures the realignment clock period matches the oscillator period, preventing distortion and phase noise damage while maintaining realignment functionality in fractional-N mode
Solution Approach 2:
The patent inverts the traditional realignment clock generation approach. Rather than deriving the realignment clock from the reference clock (top-down approach), the invention derives it from the feedback dividing clock (bottom-up approach). This inversion ensures proper synchronization with the oscillator and eliminates the phase noise problem
2Ease of operation
If realignment clock is forced to inject signal into oscillator in fractional-N mode, then realignment can be performed, but oscillator period is distorted
Solution Approach 1:
The patent changes the period parameter of the realignment clock to match the oscillator period exactly. By generating the realalignment clock from the feedback dividing clock with the same period, the injection operation can proceed without distorting the oscillator period, thus maintaining precision while enabling operation
3Adaptability or versatility
If traditional realignment technique is used, then integer-N mode operation is supported, but fractional-N mode operation is not supported
Solution Approach 1:
The patent creates a universal realignment clock generation method that works for both integer-N and fractional-N modes. By deriving the realignment clock from the feedback dividing clock rather than the reference clock, the system achieves multi-functionality - supporting both operating modes while maintaining phase noise performance in fractional-N mode
Data Source
AI summary
Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.