Fractional-N PLL Realignment Using Feedback-Derived Clocking
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Solution Overview
Problem
Traditional realignment techniques in PLL circuits are limited to integer-N mode and damage phase noise when applied to fractional-N mode, as they distort the oscillator period due to the use of a reference clock-generated realignment clock.
Innovation Solution
A new realignment clock (RLP) is generated with a period duplicated from the feedback dividing clock, allowing for improved phase noise performance in fractional-N mode by aligning with the oscillator clock, using a digital-to-time converter and delayed-locked loop to adjust the oscillator period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional realignment technique is applied to fractional-N mode, then realignment operation can be performed, but phase noise is damaged due to oscillator period distortion
Solution Approach 1:
The patent changes the fundamental parameter of the realignment clock by deriving it from the feedback dividing clock instead of the reference clock. This parameter change allows the realignment clock to have the correct frequency relationship with the VCO in fractional-N mode, enabling realignment without damaging phase noise performance
Solution Approach 2:
The feedback dividing clock serves as an intermediary between the reference clock and the realignment clock. By using the feedback dividing clock as the source for generating the realignment clock, the system achieves proper synchronization with the VCO while avoiding the harmful effects of using the reference clock directly
2Adaptability or versatility
If realignment clock is generated from reference clock, then realignment can be implemented in integer-N mode, but the technique is limited and cannot be properly applied to fractional-N mode
Solution Approach 1:
The patent creates a universal realignment clock generation method that works for both integer-N and fractional-N modes. By deriving the realignment clock from the feedback dividing clock rather than the reference clock, the system achieves multi-functionality and can properly operate in different PLL modes without compromising performance
3Reliability
If realignment clock forces signal injection into oscillator in fractional-N mode, then realignment operation occurs, but oscillator period is distorted
Solution Approach 1:
The patent changes the frequency parameter of the realignment clock to match the feedback dividing clock frequency. This parameter adjustment ensures that when the realignment clock injects signals into the VCO, the oscillator period remains stable and undistorted, while still achieving proper realignment operation
Data Source
AI summary
Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.