Fractional-N PLL Reference Delay for Simpler TDC Phase Detection
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Solution Overview
Problem
The design of digital fractional frequency-division phase-locked loops faces challenges in reducing the time domain range input to the time-to-digital converter (TDC), which complicates the design and increases the resolution requirements, making it difficult to meet the necessary precision and range simultaneously.
Innovation Solution
A control apparatus is introduced to perform delay processing on the active edge of the reference clock based on the frequency control word and frequency division control word, aligning the active edges of the delayed reference clock and feedback clock, thereby reducing the time domain input range for the TDC and simplifying its design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital fractional frequency-division phase-locked loop is designed without delay processing on the reference clock, then the structure is simpler, but the time domain range input to the TDC increases, complicating the design and increasing resolution requirements
Solution Approach 1:
The patent applies preliminary action by performing delay processing on the reference clock signal before it reaches the TDC. The control apparatus calculates a delay amount based on the fractional frequency control word and applies this delay in advance, so that when the TDC receives the delayed reference clock and the feedback clock, their time domain range is already reduced. This preliminary delay adjustment simplifies the TDC design and reduces its resolution requirements without adding significant complexity to the overall system.
2Ease of manufacture
If the TDC input time domain range is reduced without delay processing, then the TDC design is simpler, but the alignment between reference clock and feedback clock active edges deteriorates, affecting phase discrimination accuracy
Solution Approach 1:
The patent employs feedback by using the fractional frequency control word (which determines the frequency division ratio) to calculate and apply an appropriate delay to the reference clock. This feedback-based delay adjustment ensures that the delayed reference clock and feedback clock have well-aligned active edges, maintaining accurate phase discrimination at the TDC input. The delay amount is dynamically determined based on the operating conditions, ensuring both ease of TDC design and accurate phase measurement.
3Measurement precision
If delay processing is applied to the reference clock based on frequency control words, then the TDC time domain input range is reduced, but the control apparatus complexity increases
Solution Approach 1:
The patent applies parameter changes by utilizing the existing fractional frequency control word (which already contains fractional part information) to determine the delay amount. Instead of introducing a completely new control mechanism, the invention repurposes an existing control parameter (the fractional frequency control word) to govern the delay processing. This approach reduces the control apparatus complexity because it reuses existing control signals and parameters rather than adding independent control systems.
Data Source
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AI summary
A method for controlling a digital fractional frequency-division phase-locked loop and a phase-locked loop are disclosed. The phase-locked loop includes a control apparatus, a TDC, a DLF, a DCO, a DIV, and an SDM. The control apparatus performs delay processing on an active edge of a reference clock according to a frequency control word and a frequency division control word to obtain a delayed reference clock; and sends the delayed reference clock to the TDC so that the TDC performs phase discrimination processing on the delayed reference clock and a feedback clock. A control apparatus added to a phase-locked loop may perform delay processing on a reference clock according to a current frequency control word and a current frequency division control word, so that a feedback clock and a delayed reference clock have approximate active edges corresponding time. In this way, the TDC only needs to process phase discrimination signals within a relatively small time domain input range. This greatly reduces design difficulty of the TDC and lowers a requirement on a resolution of the TDC, and makes design of the TDC simple and free, thereby ensuring convenience, ease, and efficiency in design of a phase-locked loop.