Fractional-N PLL Using Sigma-Delta Division for Low Quantization Noise
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Solution Overview
Problem
Phase locked loop (PLL) devices face limitations in fractional division operations during sub-sampling, leading to deteriorated clock generator performance due to limited resolution and quantization noise.
Innovation Solution
A phase locked loop device incorporating a frequency modulating circuit to generate a reference signal by multiplying the input signal's frequency, a sigma-delta modulator to provide division ratio information, and a PLL circuit that performs phase-locking operations based on fractional division using this information, thereby improving noise characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sub-sampling operation is used to improve noise characteristics, then phase locking performance is improved, but fractional division operation becomes limited
Solution Approach 1:
The patent segments the fractional division operation into multiple integer division steps. Instead of performing a single fractional division, the system divides the clock signal through multiple stages of integer division, where each stage divides by an integer value. This allows fractional division to be achieved through combination of integer divisions, thereby enabling fractional division capability while maintaining sub-sampling operation for noise reduction.
2Adaptability or versatility
If digital to time converter is used to enable fractional division, then fractional division capability is improved, but quantization noise increases
Solution Approach 1:
The patent replaces the digital-to-time converter mechanism with a purely digital integer division-based fractional division system. Instead of using a DAC that introduces quantization noise, the system uses multiple integer dividers working in combination to achieve fractional division ratios. This substitution eliminates the quantization noise source while maintaining fractional division capability through mathematical combination of integer divisions.
3Device complexity
If limited resolution is used in sub-sampling, then circuit complexity is reduced, but clock generator performance deteriorates
Solution Approach 1:
The patent introduces dynamic adjustment capability through multiple division ratio selections in each division stage. The system can dynamically change division ratios based on required output frequency, allowing flexible frequency synthesis without increasing resolution bits. This dynamic reconfiguration of integer division ratios enables high-performance frequency generation while keeping the circuit structure relatively simple.
Data Source
AI summary
A phase locked loop device may include: a frequency modulating circuit configured to output a reference signal obtained by multiplying a frequency of an input signal by a predetermined ratio based on the input signal; a sigma-delta modulator configured to output division ratio information on one of a plurality of division rates at a number of times proportional to a frequency of the reference signal; and a phase locked loop (PLL) circuit configured to determine whether to activate based on a command signal, and, when activated, perform a phase-locking operation based on a fractional division based on the reference signal and the division ratio information.