Fractional-N PLL Sleep Modes for Phase Lock and Clock Switching
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Solution Overview
Problem
Existing fractional-N PLLs face challenges in maintaining phase lock during sleep periods while minimizing power consumption and jitter, as they often require continuous reference clock signals and lack efficient mechanisms for hitless switching between multiple reference clocks.
Innovation Solution
The implementation of a fractional-N PLL with sleep modes that allows phase lock maintenance during sleep periods by freezing oscillator control signals and using gated or ungated output clock signals, along with a modulo-K counter and fractional phase predictor that can track phase over a large range, enabling efficient power management and hitless switching between multiple reference clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous reference clock signals are used to maintain phase lock, then phase lock stability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using sleep modes where the reference clock is gated off during intervals when phase lock can be maintained from the last locked state. The system periodically wakes to update phase information while remaining in sleep mode otherwise, converting continuous operation into periodic updates that reduce power consumption while maintaining reliability.
Solution Approach 2:
The patent applies preliminary action by pre-freezing the oscillator control signal and phase detector state before entering sleep mode, ensuring the PLL is in a known good state. This preliminary preparation allows the system to remain in low-power mode longer while guaranteeing能够快速重新锁定 when needed.
2Use of energy by moving object
If sleep modes are implemented to reduce power consumption, then power efficiency is improved, but the ability to maintain phase lock deteriorates
Solution Approach 1:
The patent segments the PLL operation into distinct active and sleep phases with clear state management. By freezing specific components (phase detector, oscillator control) while allowing others to maintain state, the system achieves power efficiency during sleep while preserving the ability to rapidly resume phase lock maintenance.
Solution Approach 2:
The patent uses an intermediary state where the phase detector output is frozen but the oscillator continues running at the last locked frequency. This intermediary configuration allows the system to reduce power consumption while maintaining frequency accuracy, serving as a bridge between full active operation and complete shutdown.
3Measurement precision
If fractional-N PLL architecture is used to improve frequency resolution, then output frequency resolution is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamics by using a dual-mode N divider that can switch between integer and fractional division ratios. This dynamic switching capability allows the system to achieve fine frequency resolution when needed while falling back to simpler integer division for coarser steps, reducing the average complexity burden.
Solution Approach 2:
The patent applies parameter changes by modifying the divider ratio parameter dynamically based on the required frequency resolution. The system adjusts between integer and fractional N values to match the resolution requirements of different operating conditions, optimizing the trade-off between precision and complexity.
4Adaptability or versatility
If multiple reference clocks are supported for flexibility, then adaptability is improved, but the ability to switch without phase discontinuity worsens
Solution Approach 1:
The patent applies preliminary action by pre-loading and synchronizing multiple reference clock sources before switching is needed. Each reference clock undergoes phase alignment and frequency verification in advance, so when switching occurs, the target reference is already prepared to maintain phase continuity without disruption.
Data Source
AI summary
A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control signal that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. A first sleep mode control signal blocks a reference clock and feedback of the oscillator clock to the counter. It may also freeze loop filter parameters and block the output clock. A second sleep mode control signal may stop the oscillator.