Fractional-N PLL Compensation Filter for Reference Spur Noise
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Solution Overview
Problem
Fractional-N phase locked loops face noise contributions from unequal successive time periods in reference clocks, which manifest as reference spurs in the output clock, and existing compensation blocks also introduce noise, necessitating a solution to reduce these noise contributions effectively.
Innovation Solution
A compensation block generates a compensation factor based on a correction block and filter to remove noise components, providing input to the division factor generator of the PLL, thereby reducing frequency errors in the output clock by correcting for unequal time periods and duty cycle errors in the reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a compensation block is used to compensate for unequal successive time periods in reference clock, then frequency accuracy is improved, but noise contribution increases
Solution Approach 1:
The patent extracts and removes the DC noise component from the correction signal using a DC-nulling filter. The filter specifically targets and eliminates the DC portion of the correction signal that would otherwise be injected into the VCO, thereby resolving the contradiction by maintaining frequency accuracy compensation while removing the harmful noise contribution.
Solution Approach 2:
The patent introduces a DC-nulling filter as an intermediary component between the correction signal generation and the VCO injection stages. This intermediary filter processes the correction signal to remove DC components before the signal reaches the VCO, thus mediating between the need for frequency accuracy and the need to minimize noise.
2Speed
If reference clock with unequal successive time periods is used, then frequency multiplication is achieved, but reference spurs are generated in output clock
Solution Approach 1:
The patent employs a feedback mechanism where the unequal successive time periods in the reference clock are detected and a correction signal is generated based on this detection. This correction signal is then used to adjust the VCO frequency, creating a feedback loop that compensates for the reference spurs generated by the asymmetric reference clock while maintaining frequency multiplication.
Solution Approach 2:
The patent changes the frequency parameter of the VCO dynamically based on the detected unequal time periods in the reference clock. By adjusting the VCO frequency in response to reference clock asymmetry, the system maintains accurate output frequency while compensating for the reference spurs caused by using reference clocks with unequal successive time periods.
Data Source
AI summary
Enhancing the accuracy in compensating errors caused by a reference signal with unequal successive periods in a fractional-N phase locked loop (PLL). A compensation block generates a compensation factor, and is implemented based on a correction block and a filter. The correction block generates a correction signal containing a first frequency correction factor and a second frequency correction factor for a first period and a second period constituting each pair of successive periods, with the correction signal also containing a noise component at direct current (DC). The filter operates to remove the noise component at DC from the correction signal to generate a compensation factor containing the first frequency correction factor and the second frequency correction factor. The compensation factor thus generated may be provided as an input to a division factor generator of a frequency divider block of the PLL, potentially resulting in zero error frequency synthesis.