Fractional-N PLL Divider Control for Integer Boundary Spur Reduction
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Solution Overview
Problem
Fractional-N phase locked loops (PLLs) face challenges in managing unwanted spurious frequency components, particularly integer boundary spurs, which are difficult to mitigate due to the alternation of division ratios for finer frequency resolution.
Innovation Solution
The implementation of a multi-modulus divider (MMD) controlled by a delta-sigma modulator, where a non-integer number of clock cycles are removed from the clock signal and the operating point of the modulator is adjusted to reduce low-frequency spurious energy by introducing a non-integer offset, thereby spreading noise-shaped spurious energy to higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fractional-N PLL alternates between different division ratios to achieve finer output frequency resolution, then frequency resolution is improved, but unwanted spurious frequency components are generated
Solution Approach 1:
The patent implements dynamic adjustment of the division ratio in the frequency divider circuit based on the fractional part of the target division ratio. When the fractional part exceeds a threshold, the division ratio is dynamically switched between N and N+1 in a controlled manner, allowing the system to achieve fine frequency resolution while managing spurious component generation through dynamic control rather than static alternation
Solution Approach 2:
The patent changes the operating parameters of the frequency divider by adjusting the division ratio based on the fractional part of the target value. By comparing the fractional part against a threshold and selectively switching between different division ratios (N and N+1), the system optimizes the balance between frequency resolution and spurious component suppression through parameter modulation
2Object-generated harmful factors
If integer division ratio is used in PLL, then spurious frequency components are minimized, but output frequency resolution is limited to reference clock increments
Solution Approach 1:
The system transitions from static integer division to dynamic fractional division by continuously monitoring the fractional part of the target division ratio and adjusting the divider ratio accordingly. This dynamic approach enables frequency resolution finer than the reference clock increment while keeping spurious components manageable through controlled switching
Solution Approach 2:
The patent modifies the division ratio parameter from fixed integer values to variable fractional values by introducing a threshold-based control mechanism that adjusts the effective division ratio based on the fractional part, thereby achieving sub-reference-clock frequency resolution
3Object-generated harmful factors
If fractional-N PLL uses threshold-based division ratio switching, then low-frequency spurious energy is reduced, but system complexity increases
Solution Approach 1:
The patent applies local quality by implementing threshold-based control specifically for managing the fractional part of the division ratio, while keeping the integer part handling straightforward. This localized approach to fractional part management reduces low-frequency spurious energy without requiring complete redesign of the entire PLL control system
Solution Approach 2:
The system simplifies the control complexity by changing only the critical parameter (division ratio) based on a simple threshold comparison of the fractional part, avoiding the need for complex modulation schemes while still achieving effective spurious component suppression
Data Source
AI summary
In accordance with an embodiment, a method of operating a fractional-N phase locked loop (FN-PLL) includes: dividing a first clock signal using a multi-modulus divider (MMD) based on a modulus control signal to form a frequency-divided clock signal, where the first clock signal is based on an output clock of the PLL; generating the modulus control signal based on a divider control input value using a delta-sigma modulator (DSM); and when a fractional portion of the divider control input value is within a first range of values, and repeatedly removing a first number of clock cycles from the first clock signal before dividing the first clock signal using the MMD, where the first number of clock cycles is a non-integer number of clock cycles.