Fractional PLL Clock Shifting for Multi-Band Spur Rejection
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Solution Overview
Problem
Existing frequency evasion techniques in wireless communication networks require complex processing and are costly due to limited frequency granularity, especially when multiple frequency bands need to be cleared simultaneously, as they rely on integer clock dividers and frequent adjustments during ongoing communications.
Innovation Solution
Implementing a High Frequency fractional Phased Locked Loop (HF fractional PLL) to shift the output clock frequency, allowing for high granularity in digital clocks without changing divider ratios, thereby simplifying the process and reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integer clock dividers are used to perform frequency evasion by changing divider ratios, then digital spurs can be shifted out of analog bandwidths, but the processing complexity increases and the frequency granularity is limited
Solution Approach 1:
The patent changes the fundamental parameter of frequency control from integer-based divider ratios to fractional PLL output frequencies. By using a fractional PLL, the system can achieve fine-grained frequency adjustments without the complexity of dynamically changing multiple integer divider ratios. The fractional PLL provides continuous frequency tuning capability, allowing spurs to be shifted out of analog bandwidths with a single parameter adjustment rather than complex multi-divider coordination.
2Measurement precision
If integer clock dividers are used with limited granularity, then the available frequency range is restricted, but increasing divider granularity requires the chip to cope with high clock rates which increases implementation complexity and cost
Solution Approach 1:
The patent applies parameter change by transitioning from integer divider granularity to fractional PLL frequency control. The fractional PLL inherently provides fine frequency granularity through its fractional division mechanism, eliminating the need to increase clock rates to achieve finer frequency steps. This resolves the contradiction by providing high measurement precision (frequency granularity) without the associated increase in implementation complexity.
3Reliability
If multiple frequency bands need to be cleared of spurs simultaneously, then the number of adjustments required increases, but frequent adjustments during ongoing communications increase processing complexity and power consumption
Solution Approach 1:
The patent implements a universal frequency control mechanism through the fractional PLL that can simultaneously manage multiple frequency bands. Instead of requiring separate adjustment mechanisms for each band, the fractional PLL's single frequency output can be divided to multiple clocks, and a single frequency shift operation can clear spurs across all dependent bands. This multi-functional approach reduces both the number of adjustments needed and the associated power consumption.
4Reliability
If integer divider ratios are changed frequently during ongoing communications, then spurs can be shifted out of bandwidths, but the adjustment time increases and communication efficiency decreases
Solution Approach 1:
The patent reduces adjustment time by changing from discrete integer divider ratio changes to continuous fractional PLL frequency tuning. The fractional PLL can adjust frequency continuously and rapidly without the stepwise limitations of integer dividers. This allows faster response to spur interference conditions, minimizing communication interruptions and reducing the time loss associated with frequency adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient rejection of spurs from analog bandwidths by tuning a single parameter, the HF fractional PLL output clock frequency, providing high granularity and reducing the need for complex adjustments, thus improving the efficiency and cost-effectiveness of frequency evasion in multi-band wireless communication systems.
Implementation Method 1
a High Frequency fractional Phased Locked Loop (HF fractional PLL) to shift the output clock frequency
Data Source
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AI summary
A method of rejecting spurs within a chip containing analog and digital functions, the spurs being timed by an associated clock signal derived from the output signal of a High Frequency, HF, fractional Phase Locked Loop, PLL, the method comprising: - determining original analog rejection bandwidths associated with the operation of analog functions; - identifying original spurs associated with the operation of the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly; - obtaining a final analog rejection bandwidth based on the original analog rejection bandwidths; - obtaining final spurs based on the original spurs; - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and, - controlling the HF fractional PLL to shift the output frequency of said HF fractional PLL by the frequency shift.