Accumulator Fractional-N PLL Feedback for Spurious Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional accumulator-type fractional N-PLL synthesizers experience periodic phase errors between reference and feedback signals, leading to fractional spurious noise due to periodic switching of the frequency division number, which degrades output signal performance.
Innovation Solution
An accumulator-type fractional N-PLL synthesizer with a phase detector that generates UP and DN signals to correct fractional phase errors, utilizing a fractional phase error pulse generation circuit and removal circuit to reduce phase errors, thereby minimizing fractional spurious noise without the need for additional charge pump circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the frequency division number is periodically switched in an accumulator-type fractional N-PLL synthesizer, then a fractional frequency division number is realized, but periodic phase errors occur between reference and feedback signals, generating fractional spurious noise
Solution Approach 1:
The patent introduces a feedback mechanism where the accumulator output is fed back to the phase detector. The phase detector compares the reference signal with the feedback signal and generates correction pulses that are fed back to the accumulator, creating a closed-loop system that eliminates periodic phase errors and fractional spurious noise while maintaining fractional frequency division capability
Solution Approach 2:
The phase detector acts as an intermediary element between the reference signal and the accumulator. It processes the phase difference information and generates correction signals that mediate the interaction between the reference clock and the VCO feedback, enabling error correction without disrupting the fractional division operation
2Object-generated harmful factors
If a delta-sigma modulator is used to switch frequency division number, then fractional spurious is noise-shaped toward higher frequencies, but low-frequency noise from LPF and VCO cannot be sufficiently removed, degrading output signal performance
Solution Approach 1:
The patent extracts and removes the delta-sigma modulator from the system, replacing it with an accumulator-based approach. This eliminates the noise-shaping function that pushes fractional spurious to high frequencies, allowing the LPF to effectively filter low-frequency noise while maintaining fractional frequency division capability
Solution Approach 2:
The patent changes the operating parameters of the system by removing the modulator and using direct accumulator switching. This allows the LPF cutoff frequency to be optimized for low-frequency noise removal rather than being constrained by the need to pass high-frequency noise-shaped spurious components
3Object-generated harmful factors
If additional charge pump circuits are added to correct phase errors, then fractional spurious noise is reduced, but device complexity increases
Solution Approach 1:
The phase detector performs multiple functions: it detects phase differences, generates correction pulses for the accumulator, and enables error feedback. This multi-functional approach eliminates the need for separate charge pump circuits dedicated to error correction, reducing device complexity while maintaining noise reduction capability
Solution Approach 2:
The patent merges the phase detection and error correction functions into a single integrated feedback loop. The correction pulses generated by the phase detector are directly combined with the accumulator operation, eliminating the need for separate charge pump circuits and reducing overall system complexity
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.