Fractional PLL Modulation Using Signed Single-Bit VCO Tuning
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Solution Overview
Problem
Conventional phase locked loops (PLLs) with dual port modulation face issues such as size mismatch, delay mismatch, and rise-fall timing skew between sigma-delta modulation tuning bits, leading to undesirable modulated RF output/spurs, especially in low power, low cost connectivity standards like Bluetooth LE and GMSK modes, which result in idle tones due to DC stimuli.
Innovation Solution
A PLL with a high port fractional modulator using a sigma-delta modulator and a binary-to-thermometric converter to generate a signed single-bit signal for tuning varactors, coupled with a zero-mean dithering circuit to mitigate idle tones, allowing for finer modulation fidelity and reduced spurious content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sigma-delta modulation tuning bits are used to control varactors, then finer modulation fidelity is achieved, but size mismatch, delay mismatch, and rise-fall timing skew occur between multiple sigma-delta modulation tuning bits
Solution Approach 1:
The patent divides the high port modulation into integer and fractional portions, with the fractional portion processed by a sigma-delta modulator to achieve finer modulation fidelity while managing the complexity of multiple tuning bits through structured segmentation
Solution Approach 2:
The patent employs dithering that modifies the statistical properties of the modulation signal to transform deterministic idle tones into randomized spectral content, effectively changing the parameter distribution to eliminate harmful deterministic patterns
2Adaptability or versatility
If conventional dual port modulation is used, then the PLL can be modulated, but idle tones and spurious content appear in the RF output for low power connectivity standards
Solution Approach 1:
The patent introduces dithering as an intermediary process between the sigma-delta modulator output and the varactor control, where the dithering mechanism processes the fractional modulation bits to eliminate idle tones before they reach the RF output
Solution Approach 2:
The patent converts the potentially harmful idle tones and deterministic spurious content into beneficial randomized spectral content through dithering, transforming a harmful deterministic pattern into a beneficial randomized distribution that appears as reduced spurious content
Data Source
AI summary
An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.