Fractional Program Commands for Non-Volatile Memory Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory devices are unavailable for other operations during programming, as they require consecutive program pulse and verify cycles, leading to inefficiencies and prolonged programming times.

Innovation Solution

Implementing fractional program commands that are independently executable and pipelined, allowing non-program commands like read operations to be executed concurrently during programming by dividing the programming operation into shorter, manageable steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If consecutive program pulse and verify cycles are used for programming, then programming precision is improved, but memory device availability deteriorates

Engineering Contradiction:
Improveprogramming precisionVSAvoidmemory device availability
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The programming operation is segmented into multiple independent fractional program commands, each representing a portion of the total programming steps. This segmentation allows the memory device to process one fractional command at a time while accepting and queuing additional commands, thereby maintaining programming precision through controlled incremental programming while improving device availability through pipelined operation.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If multiple program pulse and verify cycles are executed sequentially, then programming accuracy is improved, but programming time increases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Multiple fractional program commands are prepared and queued in advance before execution begins. The memory device accepts a sequence of fractional commands representing the complete programming operation, queues them for execution, and then processes them in pipelined fashion. This preliminary action eliminates idle time between programming steps and reduces total programming time while maintaining accuracy through the incremental nature of fractional commands.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pipelined execution of fractional program commands ensures continuous useful action by eliminating idle periods between programming steps. While one fractional command is being executed, the memory device is already accepting and preparing the next commands, ensuring that the programming operation progresses continuously without interruption or waiting time, thereby reducing total programming time while maintaining precision.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If the memory device is dedicated to programming operations, then programming completeness is ensured, but device utilization efficiency deteriorates

Engineering Contradiction:
Improveprogramming completenessVSAvoiddevice utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory device operates dynamically by switching between programming and non-programming operations based on the command queue state. During fractional programming operations, the device can interleave non-programming operations (such as reads or erases) with the programming sequence, allowing flexible resource utilization while ensuring programming completeness through the structured fractional command execution model.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11651823B2Fractional program commands for memory devices
Publication Date: 2023.05.16 RAMBUS INC
  • US11651823B2 patent drawing
  • US11651823B2 patent drawing
  • US11651823B2 patent drawing

AI summary

A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.