Fractional Rate Converting Filter for Wireless Transceivers
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Solution Overview
Problem
The existing DigRF standard for wireless transceivers faces challenges in performing uplink RRC pulse shaping due to the mismatch between the 3.84 MHz chip rate and the 312 MHz sample rate, requiring costly clock generation and potentially falling out of band spectrum, especially since 3.84 MHz is not an integer multiple of 312 MHz.
Innovation Solution
A fractional rate converting filter system that includes a delay line, multiplier circuit, and adder circuit, which upsamples and downsamples the input signal to achieve a desired output sample rate without additional clock generation, using a combination of delay blocks, multiplier circuits, and tap coefficient shifting to achieve a non-integer sample rate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional clock generation is used to achieve sample rate conversion, then the desired output sample rate can be achieved, but device complexity and cost increase
Solution Approach 1:
The patent introduces an intermediary fractional rate converting filter between the baseband processor and RF transceiver that performs sample rate conversion without requiring additional clock generation. The filter uses a delay line, multiplier circuit, and adder circuit to convert between non-harmonic sample rates (e.g., 3.84 Ms/s to 312 Ms/s), acting as a mediator that eliminates the need for complex additional clock generation hardware.
2Speed
If additional clock generation is used for sample rate conversion, then the desired frequency can be achieved, but the generated frequency may fall out of band spectrum
Solution Approach 1:
The fractional rate converting filter serves as an intermediary that performs precise sample rate conversion in the digital domain before RF transmission, avoiding the generation of spurious frequencies that would fall outside the band spectrum. By converting sample rates digitally rather than through additional clock generation, the system maintains frequency accuracy without creating harmful out-of-band emissions.
3Ease of manufacture
If integer multiple relationship is maintained between chip rate and sample rate, then clock generation is simplified, but flexibility in sample rate conversion is reduced
Solution Approach 1:
The patent changes the approach from maintaining fixed integer multiple relationships to using a fractional rate converting filter that can adapt to various sample rate conversions. The filter uses configurable parameters (delay line length, multiplier coefficients, adder operations) to achieve different conversion ratios, providing flexibility while keeping clock generation simple by using existing baseband clocks.
Data Source
AI summary
A fractional rate converting filter in a wireless transceiver comprising a delay line, multiplier circuit, adder circuit, and selector. The delay line receives a digital input signal at a first sample rate and has delay blocks each providing an output and receiving samples gated at a plurality of clock cycles of an integer sub-multiple frequency of a clock. The outputs are multiplied by corresponding filter tap coefficients. Each filter tap coefficient is spaced by a first integer Y. The adder circuit receives and sums the tap outputs to provide an output signal. The selector iteratively shifts the coefficients by a second integer Z. The output of each delay block is multiplied by corresponding shifted filter tap coefficients. The delay blocks are inhibited from receiving another input sample during the plurality of clock cycles. The output signal has a second sample rate at the integer sub-multiple frequency of the clock.