Fractional-Rate DFE Circuit for ISI and DC Creep Mitigation
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Solution Overview
Problem
High-speed data transmission systems face challenges due to intersymbol interference (ISI) and DC creep, which are exacerbated by non-ideal transmission channels, leading to errors in data sensing, especially when using fractional-rate clocks with existing decision feedback equalization (DFE) circuits.
Innovation Solution
The implementation of DFE circuits that operate with fractional-rate clocks, such as half-rate and quarter-rate clocks, by using multiple data paths and comparators with offset reference voltages, allowing past decisions to influence current sampling decisions to mitigate ISI and DC creep, even when the clock frequency does not match the data frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional DFE circuits use integer-rate clocks (full-rate, half-rate), then the circuit structure is relatively simple and clock synchronization is straightforward, but they cannot achieve accurate data sensing when clock frequency does not match data frequency due to ISI and DC creep
Solution Approach 1:
The DFE circuit is divided into multiple independent data paths (first data path, second data path, third data path, fourth data path), each handling specific clock edges or data phases. This segmentation allows the circuit to process fractional-rate data by distributing the sampling task across multiple specialized paths, improving data sensing accuracy without requiring a completely new circuit architecture.
Solution Approach 2:
The patent extends the traditional single-clock-domain DFE to multi-clock-edge operation by utilizing both rising and falling edges of fractional-rate clocks. This dimensional extension from single-edge to multi-edge sampling enables accurate data recovery even when clock and data rates do not match, effectively adding a temporal dimension to the sampling process.
2Use of energy by moving object
If fractional-rate clocks are used to transmit data, then power consumption is reduced and clock jitter is minimized, but existing DFE circuits cannot properly sample data because the clock frequency does not match the data frequency
Solution Approach 1:
The DFE circuit dynamically adapts to fractional-rate clocks by implementing multiple data paths that can be selectively activated based on the clock edge timing. The circuit dynamically adjusts which comparators and data paths are active during each clock cycle, enabling reliable data sampling despite the mismatch between clock and data frequencies while maintaining the power efficiency of fractional-rate operation.
Solution Approach 2:
The DFE circuit uses feedback from previously sampled data to adjust the reference voltages and timing of subsequent sampling operations. This feedback mechanism compensates for the phase and frequency mismatches introduced by fractional-rate clocks, ensuring that each data sample is taken at the optimal moment for accurate recovery, thereby maintaining transmission reliability.
3Measurement precision
If multiple data paths and comparators are added to support fractional-rate clocks, then data sensing accuracy improves, but the number of components and circuit complexity increases
Solution Approach 1:
The multiple comparators and data paths are designed with universal functionality, where each comparator can serve multiple purposes across different clock edges and data phases. The same basic comparator circuitry is replicated and configured for different sampling moments, allowing the system to handle fractional-rate clocks efficiently without requiring entirely separate component sets for each function, thus reducing the overall component count relative to the performance gain.
Data Source
AI summary
Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.