Fractional-Rate DFE Circuit for ISI Compensation
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Solution Overview
Problem
High-speed data transmission systems face challenges due to intersymbol interference (ISI) and DC creep, which are exacerbated by the bandwidth-limiting characteristics of transmission channels, particularly in synchronous data transfer systems using SDRAM, where fractional-rate clocks are not compatible with existing decision feedback equalization (DFE) circuits.
Innovation Solution
The implementation of DFE circuits that operate with fractional-rate clocks, such as half-rate and quarter-rate clocks, using multiple data paths and comparators with offset reference voltages to mitigate ISI and DC creep, allowing for accurate data sampling and correction even with lower frequency synchronizing clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If fractional-rate clocks are used for synchronization, then power consumption and channel loss are reduced, but existing DFE circuits cannot operate correctly
Solution Approach 1:
The DFE circuit is divided into multiple independent data paths (first data path and second data path), each capable of operating with different clock rates. This segmentation allows the system to select appropriate clock rates for each path, enabling compatibility with fractional-rate clocks while maintaining equalization functionality.
Solution Approach 2:
The circuit incorporates dynamic selection mechanisms including multiplexers and mode selection logic that allow the DFE to adapt its operating mode based on the incoming clock rate. The circuit can dynamically switch between full-rate and fractional-rate operation, making it versatile across different clock domains.
2Measurement precision
If multiple data paths with offset reference voltages are implemented, then ISI and DC creep compensation accuracy is improved, but circuit complexity increases
Solution Approach 1:
Each data path is equipped with its own offset reference voltage specifically tailored for that path's clock rate. The first data path uses one offset reference voltage while the second data path uses a different offset reference voltage, optimizing each path for its specific operating conditions and improving overall sensing accuracy.
Solution Approach 2:
The DFE circuit uses feedback from previously decided data bits to adjust and compensate for ISI and DC creep in current data sampling. The offset reference voltages are determined based on feedback from prior decisions, creating a closed-loop system that continuously improves measurement precision.
Data Source
AI summary
Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.