Fractional Re-Timing for Accurate RTT Time-of-Departure Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing frame synchronization detection methods in wireless personal area networks (PANs) face radio interference issues when operating at non-integer sample rates, affecting the accuracy of time of departure (ToD) estimation for round trip time (RTT), which is crucial for secure keyless entry and BLE distance estimation.

Innovation Solution

A data re-sampling circuit is employed to generate a sampled stream of data at a local oscillator (LO) frequency, followed by a fractional conversion to a crystal oscillator (XO)-integer-divided sample rate, using a re-timer engine and comparator circuit to accurately locate the ToD marker within the frame delimiter, thereby enabling precise RTT estimation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If frame synchronization detection is performed at non-integer sample rates, then timing flexibility is improved, but radio interference occurs affecting ToD estimation accuracy

Engineering Contradiction:
Improvetiming flexibilityVSAvoidToD estimation accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary processing stage between the received signal and the frame synchronization detection. A rational sample rate converter converts the received signal from non-integer sample rate to integer sample rate, and a time interpolation mechanism compensates for the timing offset. This intermediary approach allows the system to maintain flexibility in handling non-integer sample rates while avoiding radio interference by performing detection at integer sample rates.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If frame synchronization detection is performed at integer sample rates, then radio interference is avoided, but timing flexibility and adaptability are reduced

Engineering Contradiction:
ImproveToD estimation accuracyVSAvoidtiming flexibility
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent performs preliminary time interpolation and sample rate conversion before frame synchronization detection. By pre-compensating for the timing offset and converting to integer sample rates beforehand, the system enables accurate ToD estimation at integer sample rates while still accommodating non-integer sample rate inputs. This preliminary action ensures that the detection stage operates under optimal conditions without sacrificing adaptability.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If rate adaptation is implemented for non-integer sample rates, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvesample rate compatibilityVSAvoidsignal processing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the signal processing into distinct functional blocks: a rational sample rate converter block that handles the non-integer to integer conversion, a time interpolation block that compensates for timing offsets, and the frame synchronization detection block. This segmentation allows each block to be optimized independently and simplifies the overall system design by separating the complex rate adaptation functions from the detection functions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12477496B2Estimating time of departure for round trip time with rate adaptation
Publication Date: 2025.11.18 INFINEON TECHNOLOGIES AMERICAS CORP
  • US12477496B2 patent drawing
  • US12477496B2 patent drawing
  • US12477496B2 patent drawing

AI summary

A device includes a transmitter to generate a sampled stream of data for a packet at a first sample rate. A data re-sampling circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate, and a time-shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A comparator circuit uses the re-sampled data values to match the re-sampled data values to a corresponding data value detected in the data pattern in the frame delimiter. A timing logic uses the plurality of re-timer values and the location of the marker in the data pattern in a timing calculation.