Fractional Sampling Filter Using Master-Clock Interpolation
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Solution Overview
Problem
Conventional fractional up-sampling filters require a high clock rate for the entire digital data stream, leading to inefficiency and spurious effects, and increase power consumption, particularly in portable devices.
Innovation Solution
A fractional sampling filter that eliminates the need for a high clock rate across the entire data stream by deriving different clock rates from a master clock, allowing for interpolation-based conversion of digital data rates without additional filtering stages, thereby reducing frequency spurs in the receiving band.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the sampling rate is doubled to remove frequency spurs in the receiving band, then the frequency spurs are moved to the next adjacent band, but the power consumption increases significantly
Solution Approach 1:
The patent applies parameter changes by using fractional up-sampling factors (M/N) instead of simple integer doubling. The sampling rate is increased by a fraction rather than a full integer multiple, which reduces the power consumption compared to doubling while still effectively moving frequency spurs away from the receiving band. The filter processes data at this fractional rate to achieve the desired spectral separation.
Solution Approach 2:
The patent uses partial action by applying a fractional up-sampling factor that is less than full doubling (M/N where N>1). This partial increase in sampling rate is sufficient to move frequency spurs away from the receiving band without requiring the full power consumption of complete doubling, thus achieving the harmful factor reduction with reduced energy cost.
2Object-affected harmful factors
If fractional up-sampling is performed by up-sampling to a common multiple higher clock rate and then down-sampling, then the frequency spurs are reduced, but the process is inefficient and introduces spurious effects
Solution Approach 1:
The patent extracts and removes the unnecessary intermediate high-clock-rate processing stage from the conventional fractional up-sampling approach. By directly implementing filtering at the fractional up-sampled rate without first converting to a common multiple higher clock rate, the patent eliminates the inefficient round-trip conversion process that introduces spurious effects and reduces productivity.
Solution Approach 2:
The patent segments the up-sampling and filtering operations into a single integrated stage operating at the fractional rate, rather than dividing the process into separate up-sampling to common multiple, filtering, and down-sampling stages. This segmentation eliminates the intermediate high-rate processing that causes inefficiency and spurious effects.
3Measurement precision
If the entire digital data stream is processed at a high clock rate, then the sampling accuracy is improved, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent applies local quality by processing only the necessary portions of the data stream at the higher fractional sampling rate, rather than forcing the entire digital data stream through high-speed circuitry. This localized high-precision processing achieves the required sampling accuracy for spur reduction while keeping the overall circuit complexity manageable.
Data Source
AI summary
A fractional up-sampling filter is configured to convert a lower data rate to a higher data rate by using methods of interpolation to generate output digital data that corresponds to the higher data rate. For example, if the higher data rate output is 4/3 of the lower data rate input, then for every three (3) digital data values originally sampled by the fractional up-sampling filter, four (4) output digital data values are generated and output from the filter. These output digital data values are obtained by methods of interpolation. Interpolation is performed using different filter coefficients depending on the relative timing of the output digital data rate versus the original sampling rate. The fractional up-sampling filter utilizes a high frequency master clock to derive the fractional relationship between the original sampling rate to the new fractional sampling rate.