Fractional Timing Resolution in Wireless Power Transmitters
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Solution Overview
Problem
Existing wireless power transmission systems face challenges in achieving high transfer efficiency due to the need for precise control of transistors, which increases cost and complexity, particularly when high-frequency clocks are required for precise control, leading to high implementation costs and power consumption.
Innovation Solution
The implementation of a phased-locked loop (PLL) circuit with a voltage-controlled oscillator (VCO) and a rising/falling edge control circuit that divides the clock signal into n portions and further subdivides them into m sub-portions, allowing for fractional timing resolution and precise control of transistor gates with a resolution greater than a full-clock period, reducing the need for high-frequency clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-frequency clocks are used to provide precise control of transistors, then power transfer efficiency is improved, but cost and complexity increase significantly
Solution Approach 1:
The clock signal is divided into multiple phases using a phase divider circuit, creating N phased clock signals from a single lower-frequency clock source. This segmentation allows precise timing control to be achieved through phase selection rather than requiring a high-frequency clock, thereby reducing system complexity while maintaining power transfer efficiency.
Solution Approach 2:
Instead of increasing clock frequency (one dimension), the patent introduces a temporal dimension by creating multiple clock phases. The precise timing control is achieved by selecting appropriate phase combinations rather than relying on high frequency, effectively trading frequency for phase diversity to reduce complexity.
2Loss of energy
If high-frequency clocks are used to provide precise control of transistors, then power transfer efficiency is improved, but implementation cost increases
Solution Approach 1:
The patent segments the clock signal into N phases using a phase divider, allowing precise transistor control to be achieved with a lower-frequency clock. This reduces the requirements for high-speed components and reduces overall implementation cost while maintaining the timing precision needed for efficient power transfer.
Solution Approach 2:
The patent changes the timing parameter from frequency-based precision to phase-based precision. By using multiple phases of a lower-frequency clock, the system achieves the same timing resolution without requiring expensive high-frequency components, thereby reducing implementation cost.
3Measurement precision
If high-frequency clocks are used to provide precise control of transistors, then timing resolution is improved, but power consumption increases
Solution Approach 1:
The clock signal is divided into N phases, allowing fine timing resolution to be achieved through phase selection rather than high frequency. This segmentation enables precise timing control with lower power consumption since the clock frequency can be reduced while maintaining the same effective timing resolution through phase diversity.
Solution Approach 2:
The patent uses periodic phase selection from the divided clock signals to achieve precise timing control. By cycling through different phase combinations rather than using a continuously high-frequency clock, the system achieves the required timing resolution with reduced average power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables sub-nanosecond PWM pulse fidelity at a lower system clock speed, achieving 1.15 ns timing resolution and reducing implementation costs and power consumption while maintaining high efficiency in wireless power transfer.
Implementation Method 1
a phased-locked loop (PLL) circuit having a voltage controlled oscillator (VCO), where the VCO is configured to produce a clock signal having a frequency n times greater than a power carrier frequency
Implementation Method 2
a voltage controlled oscillator (VCO), where the VCO is configured to produce a clock signal
Implementation Method 3
a divider circuit coupled to the VCO and configured to divide the clock signal into n portions
Implementation Method 4
a multiplexer coupled to the VCO and configured to subdivide each of the n portions into a plurality of m sub-portions
Implementation Method 5
a delay circuit configured to apply a timing delay only to fewer than all possible m values
Implementation Method 6
it converts an electrical current into an oscillating electromagnetic field using an inductor, coil, antenna, metal plate, or other coupling device
Implementation Method 7
Another coupling device at the RF receiver captures a portion of the radiated electromagnetic field (the two coils in proximity to each other form an electrical transformer), and the RF receiver then converts the received electromagnetic field back into an electrical current
Data Source
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AI summary
In systems (100) and methods for wireless power transfer with fractional timing resolution, an electrical power transmitter (101) may include: a transistor (Q1); and a rising edge control circuit (103) to control a gate of the transistor (Q1) to produce a rising edge of a pulse at a time selected with a resolution greater than a full-clock period.