Fracturable DSP Block for FPGA Throughput
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Solution Overview
Problem
Current FPGA architectures lack the flexibility to efficiently configure DSP blocks for varying data widths and operational modes, limiting their throughput and versatility.
Innovation Solution
The development of a dual/quad-fracturable DSP block design that includes fracturable multipliers, adders, and variable shifters, allowing for operation in normal, dual-fracturing, and quad-fracturing modes without losing functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DSP blocks are designed to handle input arguments of specific widths for each sub-module, then mathematical functions can be efficiently implemented, but the architecture lacks flexibility for varying data widths and operational modes
Solution Approach 1:
The DSP block is segmented into fracturable elements that can be divided into multiple smaller operational units. The multiplier can be fractured into smaller multipliers, the adder into smaller adders, and the shifter into smaller shifters, allowing the same physical block to handle different data widths by activating appropriate segments
Solution Approach 2:
The DSP block implements dynamic reconfiguration capability where the operational mode (normal, dual-fracturing, or quad-fracturing) can be changed at runtime through mode selection signals. This allows the architecture to adapt to varying data width requirements without physical reconfiguration
2Speed
If multiple DSPs are paired into wider elements, then wider mathematical operations can be handled at higher clock rates, but the number of mathematical operators that can be handled with the same physical DSP blocks decreases
Solution Approach 1:
The DSP block contains segmented operational units that can be configured in different aggregation states. When paired for wider operations, the segmented units work together as a single wide operator at higher clock rates. When fractured, the same segments operate independently as multiple narrow operators, maximizing the number of simultaneous mathematical operations
Solution Approach 2:
The DSP block achieves multi-functionality by allowing the same physical hardware to serve dual purposes: acting as a single wide operator for high-speed operations or as multiple narrow operators for parallel processing. The fracturable elements and mode selection mechanism enable this universal functionality
3Productivity
If DSP blocks are fractured into multiple narrower operators, then the number of mathematical operators increases, but the data width handling capability for each operator is reduced
Solution Approach 1:
The operational units are designed as segmented, fracturable elements where the multiplier, adder, and shifter can be divided into smaller functional segments. This segmentation enables the block to fracture into multiple narrower operators while maintaining the capability to handle different data widths through appropriate segment activation and mode selection
Solution Approach 2:
The DSP block implements dynamic mode switching between normal mode and fractured modes (dual-fracturing, quad-fracturing). This dynamic reconfiguration allows the system to adapt the data width handling capability of each operator based on the operational requirements, maintaining versatility across different fracturing scenarios
Data Source
AI summary
A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.