Fracturable LUT Structure for Low-Latency Quaternary Adders
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Solution Overview
Problem
Existing programmable chips, such as FPGAs, face inefficiencies in performing arithmetic operations due to the limitations of traditional lookup table structures, which hinder the efficient implementation of quaternary adders.
Innovation Solution
A lookup table structure is enhanced by incorporating a quaternary (4-1) adder using minimal additional logic, including an XOR gate, an AND gate, and two single-bit 2-1 multiplexers, building upon a ternary (3-1) adder architecture, allowing for efficient support of quaternary operations with minimal logic overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional lookup table structures are used in programmable chips, then design flexibility and reconfigurability are provided, but arithmetic operations such as quaternary adders cannot be performed efficiently
Solution Approach 1:
The patent combines a ternary adder architecture with minimal additional logic gates (XOR, AND, and 2-1 multiplexers) to create a quaternary adder structure. This merging allows the lookup table to perform both ternary and quaternary operations, resolving the contradiction by enabling efficient arithmetic operations while maintaining the existing programmable chip architecture.
Solution Approach 2:
The enhanced lookup table structure achieves multi-functionality by supporting both ternary and quaternary adder operations within the same hardware framework. The universal design allows the chip to adapt to different arithmetic requirements without requiring separate dedicated structures for each operation type.
2Loss of time
If quaternary adders are implemented using traditional binary or ternary adder trees, then the existing logic structure is maintained, but the number of levels and latency increase
Solution Approach 1:
The quaternary adder is segmented into distinct functional components: a ternary adder core and minimal additional logic units (XOR gate, AND gate, two 2-1 multiplexers). This segmentation allows each component to perform its specific function efficiently, reducing overall latency compared to traditional binary or ternary adder trees that would require more levels to achieve the same quaternary functionality.
Solution Approach 2:
The patent transitions from binary/ternary addition dimensions to quaternary addition by introducing a new operational dimension. The enhanced lookup table structure processes four inputs simultaneously through the combination of ternary adder logic and additional gates, effectively adding a dimensional capability that reduces the number of sequential levels required.
3Adaptability or versatility
If additional logic gates are added to support quaternary operations, then quaternary adder functionality is enabled, but logic overhead increases
Solution Approach 1:
Instead of completely redesigning the lookup table structure to support quaternary operations, the patent applies partial action by adding only the minimal necessary logic components (one XOR gate, one AND gate, and two 2-1 multiplexers) to the existing ternary adder. This partial enhancement achieves quaternary functionality with minimal logic overhead, avoiding the excessive complexity that would result from a complete structural overhaul.
Data Source
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AI summary
A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.