Fracturable PLL Clock Network for Pin-Limited ICs
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Solution Overview
Problem
Conventional phase-locked loop (PLL) architectures in integrated circuits are limited by the number of PLLs that can be bonded to chip packaging, restricting the number of PLLs that can be implemented due to the limited number of pins available for power and clock signals.
Innovation Solution
The proposed PLL architecture includes a fracture-able PLL circuit with two phase-locked loop circuits and shared output resources, along with a programmable clock network that allows efficient sharing of power and clock signals, enabling a greater number of PLLs to be implemented on the IC chip by sharing power and clock pins, and allowing flexible configuration of PLLs for different applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL architectures are used with dedicated power and clock pins for each PLL, then each PLL can operate independently and reliably, but the number of PLLs that can be implemented is limited by the available pins
Solution Approach 1:
Multiple PLL circuits share common power and clock signal distribution networks instead of requiring dedicated pins for each PLL. The patent implements a hierarchical clock distribution system where a small number of external clock pins feed into internal clock buffers that distribute synchronized clock signals to multiple PLL circuits, enabling many PLLs to be implemented with limited external pins while maintaining reliable operation through centralized power and clock management.
Solution Approach 2:
The clock distribution network and power supply infrastructure are designed to serve multiple PLL circuits simultaneously. The patent creates universal power rails and clock distribution trees that can support any number of PLL circuits within the IC, allowing the same physical infrastructure to be reused across multiple PLL instances rather than requiring dedicated resources for each PLL.
2Adaptability or versatility
If more PLL circuits are added to the IC chip, then more clocking functions and applications are supported, but the number of required power and clock pins increases
Solution Approach 1:
The patent transitions from a one-to-one mapping between external pins and PLL circuits to a many-to-one relationship by introducing internal clock distribution hierarchy. External clock pins connect to stage-1 clock buffers, which distribute to stage-2 buffers, which then feed multiple PLL circuits. This multi-layered distribution architecture allows a small number of external pins to support a large number of PLL circuits through internal signal replication and distribution.
Solution Approach 2:
The clock distribution system is segmented into multiple hierarchical stages with intermediate buffer elements. The patent divides the clock distribution function into stage-1 buffers receiving external signals, stage-2 buffers distributing internally, and final distribution to PLLs. This segmentation allows the system to scale to many PLLs while keeping the external pin count low, as each segmentation stage handles a portion of the distribution load.
3Adaptability or versatility
If shared power and clock infrastructure is implemented for multiple PLLs, then the number of pins is reduced and density increases, but the complexity of the clock distribution network increases
Solution Approach 1:
The patent introduces clock buffer circuits as intermediary elements between external clock pins and PLL circuits. These buffer circuits act as mediators that receive clock signals from external pins, perform signal conditioning and regeneration, and distribute the signals to multiple PLL circuits. The buffers simplify the overall network complexity by providing standardized interface points and signal regeneration, rather than requiring direct complex routing from each pin to each PLL.
Solution Approach 2:
The clock distribution network utilizes parameter changes in signal voltage levels and timing characteristics through buffer stages. The patent employs buffer circuits that can adjust signal parameters such as voltage swing, rise/fall times, and phase alignment to optimize signal quality for different PLL circuits. This parameter control capability manages network complexity by providing signal conditioning at each distribution stage rather than requiring complex equalization across the entire network.
Data Source
AI summary
One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.