Fragment-Level Translation for Emulation Performance

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Solution Overview

Problem

Just-In-Time (JIT) translation in emulation slows down execution due to dynamic target system code changes, particularly in systems with a main CPU and attached digital signal processors (DSPs), leading to performance issues and increased translation loads.

Innovation Solution

Fragment-level translation splits the emulation task into instruction memory emulation, main translation, and secondary processor emulation, allowing for parallel processing and efficient resource usage by grouping instructions into fragments and translating them on a fragment-by-fragment basis, reducing unnecessary code generation and retranslation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If JIT translation is used to translate target system code to host system code, then code execution capability is achieved, but execution speed decreases due to translation overhead and dynamic code changes

Engineering Contradiction:
Improvecode execution capabilityVSAvoidexecution speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the translation process into fragment-level units rather than translating entire programs. Each fragment is a discrete code segment that can be translated independently, allowing the system to translate only the necessary portions of code that are actually executed, thereby reducing overall translation overhead and improving execution speed while maintaining adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements speculative forward translation where code fragments are translated in advance before they are needed during execution. This preliminary translation action eliminates the need for on-demand translation during critical execution paths, reducing translation overhead and improving execution speed.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If dynamic target system code changes are handled by retranslation, then code updates are supported, but translation load increases and performance decreases

Engineering Contradiction:
Improvecode update supportVSAvoidtranslation efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by tracking and managing only the specific fragments of code that have changed, rather than retreating entire programs. Each fragment maintains its own translation state and validity information, allowing the system to perform minimal retranslation only for affected local regions, thereby supporting code updates while maintaining high translation efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements feedback mechanisms through code change detection and fragment validity tracking. When code changes are detected, the system uses feedback information about which fragments are affected to determine the minimal set that needs retranslation, optimizing the balance between supporting code updates and maintaining translation efficiency.

Inventive Principle:
Principle #23Feedback

3Reliability

If entire code segments are translated, then translation completeness is achieved, but unnecessary code generation increases resource usage

Engineering Contradiction:
Improvetranslation completenessVSAvoidcode generation volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies partial action by translating only the necessary portions of code (fragments) that are actually executed, rather than translating entire code segments. This selective translation approach maintains translation completeness for executed code while significantly reducing unnecessary code generation and resource usage.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8433555B2Processor emulation using fragment level translation
Publication Date: 2013.04.30 SONY INTERACTIVE ENTERTAINMENT LLC
  • US8433555B2 patent drawing
  • US8433555B2 patent drawing
  • US8433555B2 patent drawing

AI summary

Emulation of a target system with a host system is disclosed. Two or more target system code instructions may be grouped into one or more fragments. A main translation function may be implemented by translating each fragment into a corresponding set of position-independent instructions executable by the host system. A target processor may be emulated by executing the corresponding set of position-independent executable instructions with the host system.