F-RAM Current Mirror Sense Amp Rail-to-Rail Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric random access memory (F-RAM) devices face challenges in achieving rapid read times and reducing read errors due to limitations in developing a rail-to-rail voltage across the differential sense amp, particularly in 2T2C and 1T1C cell structures.
Innovation Solution
The implementation of current mirror sense amp structures and circuits that facilitate the rapid development of a rail-to-rail voltage across the differential sense amp by using current mirror transistors and negative voltage generators to enhance the cell read voltage, improving read speed and reliability in F-RAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sense amp structures are used in F-RAM devices, then device complexity is reduced, but read time increases and read errors occur due to inability to rapidly develop rail-to-rail voltage
Solution Approach 1:
The sense amp structure is segmented into multiple functional blocks including current mirror circuits, negative voltage generators, and differential sensing stages. Each block performs a specific function in developing the rail-to-rail voltage, allowing rapid read operation while maintaining manageable complexity through functional decomposition.
Solution Approach 2:
Negative voltage generators are introduced as intermediary circuits that actively pull the bitline and complement bitline voltages to extend the dynamic range. This intermediary mechanism enables the sense amp to rapidly develop rail-to-rail voltage without requiring an overly complex direct sensing structure.
2Reliability
If conventional sense amp structures are used in F-RAM devices, then device simplicity is maintained, but read errors increase due to insufficient cell read voltage
Solution Approach 1:
Negative voltage generators are activated before and during the read operation to pre-establish the voltage conditions necessary for reliable sensing. By preliminarily pulling the bitline voltages to the extended dynamic range, the sense amp is prepared to accurately detect even weak cell signals, reducing read errors before they occur.
Solution Approach 2:
The voltage parameters of the sense amp are dynamically changed during operation. The negative voltage generators adjust the bitline voltage levels to extend the dynamic range, and the current mirror circuits amplify the differential voltage signal. These parameter changes enable reliable read operation with improved noise margins and reduced read errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces read time and read errors by ensuring a consistent and increased cell read voltage across ferroelectric capacitors, enhancing the overall performance of F-RAM devices, including both 2T2C and 1T1C configurations.
Implementation Method 1
current mirror sense amp structures and circuits that facilitate the rapid development of a rail-to-rail voltage across the differential sense amp by using current mirror transistors
Implementation Method 2
using current mirror transistors and negative voltage generators to enhance the cell read voltage
Implementation Method 3
Ferroelectric random access memory (F-RAM) devices
Data Source
AI summary
A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.