FRAM Sense Amplifier Inversion for Imprint Reduction
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Solution Overview
Problem
Ferroelectric memory cells experience signal margin degradation due to imprinting, where retained polarization domains are induced during read and write operations, leading to data state degradation and reduced reliability.
Innovation Solution
A memory device with a sense amplifier configuration that includes cross-coupled transistors and inverters, which unconditionally inverts the data read from memory cells during read operations, reducing imprinting by rewriting the data as an opposite state and using XOR gates for conditional inversion, along with Error Checking and Correction (ECC) mechanisms to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read operations are performed on ferroelectric memory cells, then data can be read from the memory cells, but signal margin degrades due to imprinting from retained polarization domains
Solution Approach 1:
The patent applies inversion by reading data from ferroelectric memory cells and rewriting it in inverted form (0 becomes 1, 1 becomes 0). This inversion operation annihilates retained polarization domains that cause imprinting, thereby preventing signal margin degradation while maintaining data integrity through subsequent unconditioning logic that restores the original data state.
Solution Approach 2:
The patent converts the harmful effect of retained polarization domains (which cause imprinting and signal margin degradation) into a beneficial effect by using the read-rewrite-invert operation to annihilate these domains. The harmful retained charge is transformed into a cleaning mechanism that refreshes the memory cell state and improves reliability.
2Reliability
If data is rewritten during read operations to reduce imprinting, then signal margin is maintained, but additional circuit complexity is introduced
Solution Approach 1:
The patent merges the read operation with the rewrite operation by combining them into a single unified circuit path. The sense amplifier that detects the read data is directly coupled to the write circuitry, allowing the same data path to be used for both reading and rewriting (inverting) the data, thereby reducing the need for separate dedicated circuits.
Solution Approach 2:
The patent implements multi-functionality by designing the sense amplifier and associated circuitry to serve dual purposes: detecting read data and providing the inverted data back to the memory cell for rewriting. This universal circuit design eliminates the need for separate read and write pathways, reducing overall circuit complexity.
3Reliability
If unconditional inversion is applied to all read data, then imprinting is reduced, but data integrity may be compromised without error correction
Solution Approach 1:
The patent employs feedback mechanisms through unconditioning logic that monitors the inverted data state and determines whether inversion was actually needed. By using feedback from the read data itself and associated control logic, the system can conditionally apply or reverse the inversion operation to restore the original data state, ensuring data integrity while maintaining imprinting reduction benefits.
Solution Approach 2:
The patent changes the parameter of data state representation by inverting the logic levels (0 to 1, 1 to 0) during the read-rewrite cycle. This parameter transformation is used strategically to annihilate polarization domains, and subsequent unconditioning logic reverses this parameter change when appropriate, ensuring the original data is restored while the beneficial imprinting reduction is maintained.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces imprinting within ferroelectric capacitors, maintains signal margins, and does so without introducing speed penalties or increasing circuit complexity, ensuring reliable data storage and retrieval.
Implementation Method 1
A nonvolatile memory technology that is particularly attractive for these low power applications is the ferroelectric memory cell, which uses a ferroelectric capacitor for a nonvolatile memory element. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. A suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge.
Implementation Method 2
A memory device with a sense amplifier configuration that includes cross-coupled transistors and inverters, which unconditionally inverts the data read from memory cells during read operations
Implementation Method 3
By convention, the polarity of the ferroelectric capacitor voltage is defined as shown in FIG. 1. A stored '0', therefore, is characterized by a positive voltage at the plate line terminal with respect to the access transistor terminal. A stored '1' is characterized by a negative voltage at the plate line terminal with respect to the access transistor terminal. Coercive points VC and −VC are minimum voltages on the hysteresis curve that will degrade a stored data state.
Data Source
AI summary
Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.