FRAM Read Cycle Optimization via Elevated Plate Line Voltage
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Solution Overview
Problem
Conventional ferroelectric random access memories (FRAMs) have long cycle times due to the necessity of multiple pulses and intervals within each read cycle, which limits memory performance.
Innovation Solution
Applying an elevated plate line voltage above the array power supply voltage during the charge transfer portion of a read cycle, allowing for the elimination of one of the write-back pulses and reducing the need for separate write operations, thereby shortening cycle times without degrading read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional multiple-pulse read cycle is used, then read margin is maintained, but cycle time is long
Solution Approach 1:
The patent extracts and eliminates one of the write-back pulses from the conventional three-pulse read cycle. By removing the redundant write-back pulse that restores the '0' data state, the read cycle is shortened from multiple pulses to a single essential pulse, directly reducing cycle time while maintaining read margin through the elevated voltage approach.
Solution Approach 2:
The patent changes the voltage parameter of the plate line pulse by applying an elevated voltage above the array power supply voltage during the charge transfer portion. This parameter change enables the single pulse to achieve both read and write-back functions, eliminating the need for separate write operations and reducing cycle time while preserving read margin.
2Loss of time
If elevated plate line voltage is applied, then cycle time is reduced, but read margin may be degraded
Solution Approach 1:
The patent carefully controls the voltage parameter by applying an elevated plate line voltage above the array power supply voltage, but within a range that maintains read margin. The elevated voltage is sufficient to eliminate the need for write-back pulses and reduce cycle time, while the voltage level is controlled to prevent degradation of read margin, achieving both speed and reliability improvements.
3Reliability
If separate write operation is performed, then data state is restored, but memory cycle time increases
Solution Approach 1:
The patent merges the read operation and the write-back operation into a single integrated process. By applying an elevated plate line voltage during the charge transfer portion, the same pulse that performs the read also restores the '0' data state, eliminating the need for a separate write operation and significantly reducing memory cycle time while maintaining data integrity.
Solution Approach 2:
The elevated plate line pulse serves multiple functions simultaneously: it performs the charge transfer for reading the data state and also restores the '0' data state in cells that originally stored '0'. This multi-functional approach eliminates redundant operations and shortens the memory cycle without compromising data restoration reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces cycle times in ferroelectric memories while maintaining read margin, with minimal additional circuitry required, and eliminates the need for a separate write operation to the '0' data state, improving overall memory access performance.
Implementation Method 1
Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors
Implementation Method 2
Applying an elevated plate line voltage above the array power supply voltage during the charge transfer portion of a read cycle
Data Source
AI summary
A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state.