Frame Arbitration Circuit for Variable Packet Size Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic systems, the mismatch in frame sizes between chip-to-chip serial communications and on-chip parallel data transfer poses challenges in efficient data conversion, leading to inefficiencies and payload reduction issues when handling packets of different sizes.
Innovation Solution
An integrated circuit with an arbitration circuit that generates logical frames by concatenating packets of varying sizes, followed by a framing circuit converting these logical frames into physical frames suitable for serial transmission, allowing for flexible frame size conversion and accommodating failed lanes without integral power reductions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frame size is standardized for serial transmission, then communication reliability is improved, but payload efficiency deteriorates due to mandatory payload reduction
Solution Approach 1:
The patent segments the transmission process into two distinct stages: logical frame construction (where packets of varying sizes are concatenated to form a logical frame) and physical frame generation (where the logical frame is converted to a standardized physical frame size). This segmentation allows the system to maintain both payload efficiency in the logical layer and communication reliability in the physical layer, resolving the contradiction between these two requirements.
2Device complexity
If fixed frame size is used for serial link, then device complexity is reduced, but productivity deteriorates due to inefficient data transmission
Solution Approach 1:
The patent introduces a logical frame as an intermediary structure between the variable-size packets from functional circuit blocks and the fixed-size physical frame required for serial transmission. This intermediary allows the system to maintain a simple fixed-size physical frame interface while efficiently utilizing available bandwidth through flexible logical frame construction, thereby resolving the contradiction between device complexity and productivity.
3Adaptability or versatility
If variable packet sizes are accommodated, then adaptability is improved, but manufacturing precision deteriorates due to frame size mismatch
Solution Approach 1:
The patent implements a dynamic frame construction process where the logical frame size adapts to the total size of concatenated packets, while the physical frame size remains fixed. The arbitration circuit dynamically selects and concatenates packets of varying sizes to form logical frames, which are then dynamically adjusted during conversion to physical frames. This dynamic approach allows the system to accommodate variable packet sizes while maintaining precise frame size matching for serial transmission.
Data Source
AI summary
A method and apparatus for generating logical frames from arbitrating among packets is disclosed. An integrated circuit (IC) includes an arbitration circuit configured to generate a logical frame having a first number of bytes by selecting at least one a plurality of packets received from different functional circuit blocks. At least one of the plurality of packets is of a different data size than at least one other one of the plurality of packets. The arbitration circuit is configured to, when selecting two or more of the plurality of packets, generate the logical frame by concatenating selected packets together. The IC further includes a framing circuit configured to generate, based on the logical frame, a physical frame for an outgoing transmission over a serial communications link, wherein the physical frame comprises a second number of bytes that is less than or equal to the first number of bytes.