Frame Buffer Logic for L2 Cache Dirty Data Management
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Solution Overview
Problem
Current systems face inefficiencies in writing dirty data from Level 2 cache to DRAM, leading to increased halted read and write operations and reduced memory throughput, particularly in high-data-throughput systems like graphics systems.
Innovation Solution
A method is introduced that involves receiving dirty data notifications, determining associated bank pages, marking valid entries, and transmitting dirty data to external memory when a pre-determined threshold of cache lines with resident dirty data is reached, thereby minimizing halted operations and optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dirty data is written to DRAM immediately when generated in L2 cache, then memory throughput is improved, but the complexity of coordinating DRAM bank page pre-charging increases and halts operations occur
Solution Approach 1:
The system performs preliminary actions by pre-charging DRAM bank pages before they are needed for dirty data writes. The L2 cache monitors which bank pages will be needed soon and triggers pre-charging operations in advance, so that when dirty data needs to be written, the target bank pages are already ready to receive data, eliminating waits and halts.
Solution Approach 2:
The system implements feedback mechanisms where the L2 cache continuously monitors DRAM bank page states, dirty data accumulation, and access patterns. This feedback information is used to dynamically adjust pre-charging decisions and dirty data write timing, optimizing the balance between throughput and coordination complexity based on real-time system conditions.
2Productivity
If multiple write operations are batched to the same DRAM bank page, then memory access efficiency is improved, but the duration of halted operations increases while waiting for batch completion
Solution Approach 1:
The system dynamically adjusts the batching strategy based on real-time conditions. When DRAM bank pages are pre-charged in advance, the L2 cache can safely batch multiple dirty data writes to the same bank page, improving efficiency through consolidated transfers. The dynamic nature of pre-charging allows the system to optimize batch sizes and timing, reducing halt durations while maintaining high memory access efficiency.
3Loss of time
If the L2 cache waits for DRAM bank pages to pre-charge before writing dirty data, then memory access delays are reduced, but the number of halted read and write operations increases
Solution Approach 1:
The system performs preliminary pre-charging of DRAM bank pages based on predicted future needs and current dirty data accumulation patterns. By proactively pre-charging bank pages before they are actually needed for dirty data writes, the system eliminates the waits that would otherwise cause halted operations, allowing continuous cache throughput while ensuring bank pages are ready when needed.
Data Source
AI summary
One embodiment of the invention sets forth a mechanism for efficiently write dirty data from the L2 cache to a DRAM. A dirty data notification, including a memory address of the dirty data, is transmitted by the L2 cache to a frame buffer logic when dirty data is stored in the L2 cache. The frame buffer logic uses a page-stream sorter to organize dirty data notifications based on the bank page associated with the memory addresses included in the dirty data notifications. The page-stream sorter includes multiple sets with entries that may be associated with different bank pages in the DRAM. The frame buffer logic transmits dirty data associated with an entry that has a maximum threshold of dirty data notifications to the DRAM. The frame buffer logic also transmits dirty data associated with the oldest entry when the number of entries in a set reaches a maximum threshold.