Frame Buffer Page Management for Cache Utilization
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Solution Overview
Problem
Conventional caching solutions for frame buffers in display systems lead to inefficient cache utilization, particularly in small form factor devices, due to inadequate allocation policies that fail to fully leverage cache capacity, especially when handling both tiled and non-tiled data types.
Innovation Solution
Implementing a fixed set selection policy for allocating frame buffer pages into a cache, where each tile is ordered into a linear stream of pages, ensuring uniform distribution across the cache, thereby achieving full cache utilization without the need for data-type dependent tuning or randomization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional caching solutions allocate frame buffer pages to cache, then cache storage is provided, but cache utilization is insufficient
Solution Approach 1:
The frame buffer is segmented into multiple pages, and each page is assigned to a specific cache set based on a page-to-cache mapping relationship. This segmentation enables systematic distribution of frame buffer data across cache memory, ensuring that all cache sets are utilized during tiled rendering operations.
Solution Approach 2:
The patent introduces a new dimension of page ordering within tiles, where pages are arranged in a specific sequence (e.g., row-major or column-major order) to ensure uniform distribution across cache sets. This dimensional reorganization transforms the traditional two-dimensional frame buffer into a sequentially accessible linear stream that maps efficiently to cache memory.
2Adaptability or versatility
If caching policy is tuned to be data type dependent, then support for different data types improves, but system complexity increases
Solution Approach 1:
The patent implements a universal page-to-cache mapping mechanism that works for all data types (tiled and non-tiled) without requiring separate caching policies. The same page ordering and mapping logic applies regardless of data type, eliminating the need for complex data-type-dependent tuning while maintaining support for multiple data formats.
3Productivity
If frame buffer page assignments are randomized, then cache distribution may improve, but full cache utilization cannot be guaranteed
Solution Approach 1:
The patent performs preliminary page ordering and mapping configuration before tiled rendering begins. By pre-establishing the page-to-cache mapping relationships and ordering pages in a predetermined sequence, the system ensures that cache sets will be uniformly utilized during rendering without relying on randomization, thus guaranteeing full cache utilization.
Data Source
AI summary
Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.