Frame Buffer Timing Control for Image Processing Overflow
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Solution Overview
Problem
In variable bit rate applications, the difference in compression and decompression bit rates between frames can cause read/write overflow issues when using a single frame buffer, leading to increased costs due to the need for multiple buffers.
Innovation Solution
An image data processing apparatus and method that divides frames into horizontal line groups, using a single frame buffer with a timing controller to alternately write and read compressed data, ensuring efficient buffering without increasing frame buffer costs by controlling the write and read operations to avoid overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single frame buffer is used to store compressed data, then the frame buffer cost is reduced, but read/write overflow occurs due to different compression and decompression bit rates
Solution Approach 1:
The patent divides each frame into multiple horizontal line groups, allowing the frame buffer to store data from different frames simultaneously without overflow. By segmenting the frame data into manageable units (horizontal line groups), the system can interleave read and write operations safely, preventing read/write overflow while using a single frame buffer.
Solution Approach 2:
The patent performs preliminary actions by storing compressed data of horizontal line groups from the current frame into the frame buffer before completely processing the previous frame. This advance storage ensures that when decompression is needed, the data is already available, preventing read overflow while maintaining a single frame buffer.
2Reliability
If two frame buffers are used to prevent read/write overflow, then read/write overflow is solved, but the cost increases due to requiring two frame buffers
Solution Approach 1:
Instead of using two complete frame buffers, the patent segments the frame data into horizontal line groups and uses a single frame buffer to store these segments. This segmentation allows one frame buffer to functionally replace two complete buffers by managing data in smaller, non-overlapping units.
Solution Approach 2:
The patent introduces a new dimension of organization by grouping horizontal lines into line groups and processing them in a specific sequence. This dimensional reorganization allows the system to manage frame data more efficiently in time and space, enabling single-buffer operation that prevents overflow without requiring dual buffers.
3Productivity
If compressed data is written into the frame buffer continuously, then buffering performance is improved, but read/write overflow occurs when compression bit rate differs from decompression bit rate
Solution Approach 1:
The patent implements periodic action by alternating between writing compressed data from the current frame and reading decompressed data from the previous frame in a rhythmic cycle. The timing controller manages these periodic operations to ensure that write operations complete before read operations begin, preventing overflow while maintaining high buffering performance.
Solution Approach 2:
The timing controller provides feedback control by monitoring the completion status of horizontal line group processing and using this information to trigger appropriate write or read operations. This feedback mechanism ensures that data is written only when processing is complete and read operations are scheduled appropriately, preventing read/write overflow while maintaining continuous buffering performance.
Data Source
AI summary
An image processing apparatus includes a processing circuit and a storage system. The processing circuit generates a first processing result and a second processing result by processing a first horizontal line group of a first frame and a second horizontal line group of a second frame preceding the first frame, respectively. The storage system includes: a frame buffer; a write circuit for storing the first processing result into the frame buffer; a read circuit for reading the second processing result from the frame buffer; and a timing controller for controlling the write circuit to start storing the first processing result at a first time point not prior to a specific time point when the processing circuit finishes receiving the first horizontal line group, and controlling the read circuit to start reading the second processing result at a second time point which is prior to the specific time point.